XTNETA1570MFP datasheet(54/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

base-address registers

The base-address registers enable the host to map the device’s address space into the host-memory or

I/O-address space. The TNETA1570 only uses the base-address 0 register from the configuration block. This

follows:

BIT

NAME

FUNCTION

RESET

VALUE

Memory-space

indicator

This bit indicates whether the base address maps into the host’s memory or I/O space. This bit

is hardwired to 0 in the TNETA1570 indicating that this base address is valid only for memory

accesses. Due to the large amount amount of space required by the device, mapping into the

I/O space is not supported.

1− 2

Type

These bits indicate the size of the base address and how it can be mapped into the host memory.

These bits are hardwired to 00 in the TNETA1570 indicating that a 32-bit base-address register

is used, which can be located anywhere in memory.

Prefetchable

This bit is hardwired to 0 in the TNETA1570.

4− 19

Internally used

address bits

These bits are hardwired to all zeroes to define the size of the address space needed by the

TNETA1570, which contains 1-M locations. The system-setup software can determine the

address space needed by a PCI device by writing all ones to the base-address register, reading

the written value back, and noting which bits were cleared.

All 0s

20 − 31

Available address bits

These bits are writable by the host to allow initialization of the base address at startup.

All 0s

latency, grant, and interrupt registers

DESCRIPTION

HARDWIRED

VALUE

MAX_LAT

This specifies how often the device needs to gain access to the PCI bus in 0.25-

ms units. The typical

value of .5

ms (02h) is hardwired for the TNETA1570.

02h

MIN_GNT

This specifies the length of the burst period the device needs in 0.25-

ms units. The typical value of

0.25-

ms (01h) is hardwired for the TNETA1570.

01h

Interrupt line

The value in this 8-bit register is written by the host and indicates to which input of the system-interrupt

controller the TNETA1570 interrupt signal is connected. This register is not cleared on software reset.

00h

Interrupt signal

This register indicates which interrupt signal the device uses. This register is hardwired to a 01h in

the TNETA1570 to indicate that interrupt A is used.

01h

error and interrupt signals

parity-error (PPERR) protocol

If the TNETA1570 is mastering the bus, the data-parity-reported bit (bit 15) in the PCI configuration-space status

D If it detects a parity error during the data phase of a read transaction

D If it detects that PPERR has been asserted by the target during the data phase of a write transaction

The data-parity-detected bit (bit 8) in the PCI-configuration-space status register is set under any of the following

conditions:

D If is is acting as the PCI-bus master and it detects a data-parity error during a read transaction

D If it is acting as a PCI-bus target and it detects a data-parity error during a write transaction

D If it detects an address-parity error

XTNETA1570MFP 数据表(PDF) 54 Page - Texas Instruments

XTNETA1570MFP 数据表(HTML) 54 Page - Texas Instruments

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