XTNETA1570MFP datasheet(58/68 Pages) TI1

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TNETA1570

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH INTEGRATED 64BIT PCIHOST INTERFACE

SDNS033B − JUNE 1995 − REVISED MAY 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PRINCIPLES OF OPERATION

64-bit PCI cell-payload writes

The following table shows the PCI-bus byte/address ordering when cell-payload bytes are input to the

reassembly UTOPIA port in the order 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, . . .

The top-down order of the following chart represents the time order of 64-bit word writes by the TNETA1570.

PCI ADDRESS

PCI ADDRESS BITS

×10

×18

×20

TNETA1570 accesses to control structures in host memory

The PCI accesses in the big-endian configuration section apply to cell-payload transfers when segmenting or

reassembling packets. All other host-memory accesses by the TNETA1570 are to entities which are defined

as control structures. These control structures are the transmit-buffer descriptors, packet-segmentation rings,

transmit-completion rings, receive-buffer descriptors, receive free-buffer rings/FIFO, and receive-completion

rings.

Accesses to control structures by the TNETA1570 are 32 bit only. Big- or little-endian configuration does not

affect control structures since the information contained in each 32-bit word of a control structure is bit defined

in this document.

access to control memory via the PCI interface

The control memory is accessed via the PCI interface in full 32-bit words. Byte enable is not supported. All four

bytes in a 32-bit-word in the control memory are read or written to in a single instruction. If none of the byte

enables are asserted for a write instruction, none of the data in the 32-bit word is altered. If any byte enable is

asserted, the entire 32-bit word is overwritten.

internal registers and counters

The TNETA1570 has several internal registers for storing configuration and status information, as well as

keeping track of certain statistics. The following internal registers have been previously defined for the

TNETA1570 device:

DESCRIPTION

Bits 31 − 16

Bits 15 − 0

Offset Address

From PCI-Base

Address for

TNETA1570 Reserved

Area (= 3200 hex)

Configuration Register

0000h

Status Register

0004h

Interrupt-Mask Register

0008h

Reassembly-Global-Timer Register

RAT Cycle-Counter Register

000C

RX Unknown Register

0010h

TX Completion Ring Without Interrupt-Size Register

TX Completion Ring With Interrupt-Size Register

0014h

RX Completion Ring Without Interrupt-Size Register

RX Completion Ring With Interrupt-Size Register

0018h

XTNETA1570MFP 数据表(PDF) 58 Page - Texas Instruments

XTNETA1570MFP 数据表(HTML) 58 Page - Texas Instruments

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