TNETA1500

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS021D – MARCH 1994 – REVISED JANUARY 1998

3

POST OFFICE BOX 655303

functional block diagram

RSDT

RSDC

CKRECBP

CLKLOOP

TSDC

TSCT

CKGENBP

TXREFCK

TXHCKT

TLB

TSCC

TSDT

TXHCKC

RSCT

RSCC

RESET

OE

TD0–TD7

A0–A7

Clock

Recovery

Framing and

Serial-to-Parallel

Conversion

Descrambling,

B1-Parity,

Alarm

Generation

Demux

ATM-Cell

Extraction

and

Descrambling

Controller

Interface

ATM-Cell

Scrambling

and

Cell Insertion

RD0–RD7

RCKI

RXCELL

RRE

RXFE

Mux

D0–D7

READY

RD/WR

INTR

SEL

TCKI

TXCELL

TWE

TXAF

Scrambling

and

B1-Parity

Generation

Parallel-to-Serial

Conversion

Clock

Generation

LOF

FLB

OOF

B1ERR

LAIS

LOSRD

LOCA

LFERF

8

8

8

8

FLAGT

FLAGC

CRCAP

LOS

LOP

CGCAP

0.1-

µF Capacitor

Connected Externally

SDHENABLE

0.1-

µF Capacitor

Connected Externally

Receive Operation

Transmit Operation

8KHZREF