TNETA1500

155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER

SDNS021D – MARCH 1994 – REVISED JANUARY 1998

10

POST OFFICE BOX 655303

interrupt registers

The interrupt registers located at hex addresses 00, 01, and 02 contain information on the condition of the

receive-data stream that causes INTR to become active low. The coding for the interrupt registers is given in

Table 4.

Table 4. Interrupt-Register Coding

CAUSE OF INTERRUPT

IR1 CODING

(ADDRESS 00)

IR2 CODING

(ADDRESS 01)

IR3 CODING

(ADDRESS 02)

B1 parity error

XXXX XXX1

—

—

B2 parity error

XXXX XX1X

—

—

B3 parity error

XXXX X1XX

—

—

Loss-of-cell alignment

XXXX 1XXX

—

—

Loss-of-incoming signal

XXX1 XXXX

—

—

Out of frame

XX1X XXXX

—

—

Loss of frame

X1XX XXXX

—

—

Loss-of-optical carrier

1XXX XXXX

—

—

Line AIS

—

XXXX XXX1

—

Line FERF

—

XXXX XX1X

—

Loss-of-receive data

—

XXXX X1XX

—

Loss of pointer

—

XXXX 1XXX

—

Path AIS

—

XXX1 XXXX

—

B1 block-error overflow

—

XX1X XXXX

—

B2 block-error overflow

—

X1XX XXXX

—

B3 block-error overflow

—

1XXX XXXX

—

B1 CV overflow

—

—

XXXX XXX1

B2 CV overflow

—

—

XXXX XX1X

B3 CV overflow

—

—

XXXX X1XX

Path RDI

—

—

XXXX 1XXX

Path FERF

—

—

XXX1 XXXX

The alarm conditions or errors set bits in the interrupt register that cause INTR to go active low. All of these

conditional actions are associated with the receive-data stream and are described below.

LOS, OOF, LOF, LAIS, LOP, LFERF, LOCA, and LOSRD

These alarm conditions cause an external signal to go active and set a bit in one of the interrupt registers

(see terminal functions table for description of the individual alarms). The status of the bit in the interrupt register

for these alarms mirrors the status of the external signal. For example, as long as an LOF condition exists, both

LOF and the LOF bit in IR1 (the value for LOF is x1xx xxxx) are set. When the logic in the TNETA1500 detects

that the LOF condition has cleared, the external output and the status bit in the interrupt registers are cleared.

A change in the status bit in the interrupt registers for these alarms causes INTR to go active low. When the

status bit makes a low-to-high transition, INTR goes active low. INTR also goes active low when the status bit

makes a high-to-low transition. Reading the interrupt register does not clear the status bit for these particular

alarms. However, INTR goes inactive high on a read of any of the interrupt registers.