ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

3

POST OFFICE BOX 1443

description (continued)

Compliant with IEEE Standard 1149.1 (JTAG), the TNETE100A provides a five-pin test-access port that is used

for boundary-scan testing.

The TNETE100A is available in a 144-pin thin quad flat package and quad flat package.

differences between TNETE100 and TNETE100A:

The TNETE100A implements the CIS pointer register as defined in the PC card standard. This register can be

found in the PCI configuration registers at offset 28h. For other differences between the TNETE100 and

TNETE100A, consult the

ThunderLAN Programmer’s Guide (literature number SPWU013).

pin assignments

PCM AND PGE PACKAGES

( TOP VIEW )

ARCVN

VDDR

ARCVP

FRCVN

VDDR

FRCVP

VSSR

VSST

AXMTN

AXMTP

FXMTN

FXMTP

VDDT

MRST

VDDL

MDIO

VSSL

MDCLK

MRXER

MRXDV

VSSI

MRXD3

MRXD2

MRXD1

VDDL

MRXD0

MRCLK

MCRS

MCOL

VDDL

MTXER

MTXEN

MTXD3

VSSL

MTXD2

MTXD1

PAD24

PC/BE3

VSSI

PIDSEL

PAD23

VDDI

PAD22

PAD21

PAD20

VSSI

PAD19

PAD18

PAD17

VDDI

PAD16

PC/BE2

PFRAME

VSSL

PIRDY

PTRDY

PDEVSEL

VDDL

PSTOP

PPERR

PSERR

VSSI

PPAR

PC/BE1

PAD15

PAD14

VSSI

PAD13

PAD12

VDDI

PAD11

PAD10

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