数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

TNETE100A 数据表(PDF) 12 Page - Texas Instruments

部件名 TNETE100A
功能描述  PCI ETHERNETE CONTROLLER SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
PDF  26 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETE100A 数据表(HTML) 12 Page - Texas Instruments

Back Button TNETE100A Datasheet HTML 8Page - Texas Instruments TNETE100A Datasheet HTML 9Page - Texas Instruments TNETE100A Datasheet HTML 10Page - Texas Instruments TNETE100A Datasheet HTML 11Page - Texas Instruments TNETE100A Datasheet HTML 12Page - Texas Instruments TNETE100A Datasheet HTML 13Page - Texas Instruments TNETE100A Datasheet HTML 14Page - Texas Instruments TNETE100A Datasheet HTML 15Page - Texas Instruments TNETE100A Datasheet HTML 16Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 26 page
background image
ThunderLAN
™ TNETE100A
PCI ETHERNET
™ CONTROLLER
SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN
SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, VDD (see Note 2)
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (see Note 2)
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range
– 0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation
1.15 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC
0
°C to 95°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-ambient package thermal impedance,
airflow = 100 LFPM, TJA(100) PGE
45.4
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-ambient package thermal impedance,
airflow = 0 LFPM, TJA(0) PGE
51
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-ambient package thermal impedance,
airflow = 0 LFPM, TJA(0) PCM
41.4
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
airflow = 100 LFPM, TJA(100) PCM
38.0
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction-to-case package thermal impedance, TJC
0.22
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
–65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground.
The recommended operating conditions and the electrical characteristics tables are divided into groups,
depending on pin function:
D PCI interface pins
D Logic pins
D Physical layer pins
The PCI signal pins are operated in one of two modes shown in the PCI tables.
D 5-V signal mode
D 3-V signal mode
recommended operating conditions (PCI interface pins only) (see Note 3)
3-V SIGNALING
OPERATION
5-V SIGNALING
OPERATION
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
VDD
Supply voltage (PCI)
3
3.3
3.6
4.75
5
5.25
V
VIH
High-level input voltage
0.5
 VDD‡
VDD + 0.5‡
2.0
VDD + 0.5
V
VIL
Low-level input voltage, TTL-level signal (see Note 4)
– 0.5‡
0.5‡
– 0.5
0.8
V
IOH
High-level output current
TTL outputs
– 0.5‡
–2
mA
IOL
Low-level output current (see
Note 5)
TTL outputs
1.5‡
6
mA
‡ Specified by design SPICE IV Curve (please refer to PCI specification revision 2.1, section 4.2, paragraph 2 for explanation)
NOTES:
3. PCI interface pins include PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ, PGNT,
PCLK, PPAR, PRST, PINTA, PAD[31 : 0], and PC/BE[3 : 0].
4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com