ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

10

POST OFFICE BOX 1443

BIOS ROM / LED driver interface (BRI)

The BRI addresses and reads data from an external BIOS ROM through a multiplexed byte-wide bus. The ROM

address / data pins also can be multiplexed to drive external status LEDs.

configuration and I / O memory registers (CIOREGS)

The CIOREGS reside in the configuration space, which is 256 bytes in length. The first 64 bytes of the

configuration space comprise the header region, which is defined explicitly by the PCI standard.

DMA controller (DMAC)

The DMAC is responsible for coordinating TNETE100A requests for mastership of the PCI bus. The DMAC

provides byte-aligning DMA control, allowing byte-size fragmented frames to be transferred to any byte address

while supporting 32-bit data streaming.

protocol handler (PH)

The PH implements the serial protocols of the network. On transmit, it serializes data, adds framing and CRC

fields, and interfaces to the network PHY. On receive, it provides address recognition, CRC and error checking,

frame disassembly, and deserialization. Data for multiple channels is passed to and from the PH by way of

circular buffer FIFOs in the FSRAM controlled through FPREGS. The PH supports an MII that is compatible with

the IEEE 802.12 and IEEE 802.3u logic.

media-independent interface (MII)

The MII provides both MAC-level 100 Base-T (IEEE 802.3u) and 100VG-AnyLAN (IEEE 802.12) controller

functions to external PHY chips that handle the PHY functions for 100-Mbps CSMA / CD and demand priority.

The MII also is used to communicate with the on-chip 10 Base-T PHY which is located at address 0x1F.

10 Base-T physical layer (PHY)

The PHY acts as an on-chip front-end providing physical layer functions for 10 Base-5 (AUI), 10 Base-2 and

10 Base-T (twisted pair). The PHY provides Manchester encoding / decoding from MII nibble-format data, smart

squelch, jabber detection, link pulse detection, autopolarity control, 10 Base-T transmission waveshaping, and

antialiasing filtering. Connection to the AUI drop cable for the 10 Base-T twisted pair is made through simple

isolation transformers (see Figure 2) and no external filter networks are required. Suitable external termination

components allow the use of either shielded or unshielded twisted-pair cable (150

W or 100 W). Some of the

key features of the on-chip PHY are listed as follow: