ST802RT1B datasheet(14/58 Pages) STMICROELECTRONICS

14 / 58 page

Pin description

ST802RT1A, ST802RT1B

14/58

Doc ID 17049 Rev 1

Pin n°

Name

Type

Description

Xtal out. 25 MHz reference clock output. When an external 25 MHz crystal is

used, this pin is connected to one of its terminals. If an external clock source is

used, then this pin should be left open.

TXP

TXN

I/O

Differential transmit outputs (100Base-TX, 10Base-T). These pins output

directly to the transformer. When MDIX is enabled, they can work as RXP/RXN

SDP

SDN

Signal detect (ST802RT1B version only) see Table 5.

Connect a 100

Ω resistor between TXn and VCCA and between TXp and

VCCA to achieve the pseudo-emitter coupled logic (PECL) levels for the optical

transmitter. The PECL logical low level (PECLLOW) is approximately VCC-1.7 V,

the PECL logical middle level (PECLMID) is approximately VCC-1.32 V and the

PECL logical high level (PECLHIGH) is approximately VCC-0.9 V.

RESERVED in ST802RT1A the pins must be grounded through a 1.2 k

resistor

RXP

RXN

I/O

Differential receive inputs (100Base-TX, 10Base-T). These pins directly

output to the transformer. When MDIX is enabled they can work as TXP/TXN

IREF

Reference resistor/DC regulator output. Reference resistor connecting pin

for reference current, directly connect a 5.25 k

Ω ± 1% resistor to VSS.

LED_LINK

O, PU

Link LED. In Mode 1 and Mode 2 this pin indicates the status of the link. The

LED is ON when the link is good.

LED_SPEED

O, PU

Speed LED. This pin is driven on continually when 10Mb/s or 100Mb/s network

operating speed is detected.(All modes -> ON: 100Mb/s, OFF: 10Mb/s)

LED_ACT

O, PU

Activity/collision LED. This pin is driven on continually when a full-duplex

configuration is detected. This pin is driven on at a 20 Hz blinking frequency

when a collision status is detected in the half-duplex configuration. (Mode 2 ->

BLINK: activity - Mode 1 -> ON: full-duplex, BLINK: collision)

RESET

Reset (active-low). This input must be held low for a minimum of 1 ms to reset

the ST802RT1x. During power-up, the ST802RT1x is reset regardless of the

state of this pin. Reset is not complete before 1 ms plus an MDC transition.

9PWRDWN

I, PU,

Power-down. This pin is an active low input in this mode and should be

asserted low to put the device in a power-down mode. During power-down

mode, TXP/TXN outputs and all LED outputs are 3-stated, and the MII interface

is isolated. The power-down functionality is achievable by software by asserting

bit 11 of register RN00.

10, 11

RESERVED

(No connection) - Should be pulled low for normal operation through an external

resistor of 2.2 k

Digital power pins

OVDD

Supply

IO ring power supply (3.3 V)

36, 41

DVDD

Supply

Digital power (3.3 V)

12, 33,

GND

Ground Digital ground

Analog power pins

4, 13,

22, 24

VCCA

Supply

Analog power supply

Table 4.

Pin functions of the ST802RT1x (continued)

ST802RT1B 数据表(PDF) 14 Page - STMicroelectronics

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ST802RT1B 数据表(PDF) 14 Page - STMicroelectronics

ST802RT1B 数据表(HTML) 14 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

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