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ST802RT1B 数据表(PDF) 50 Page - STMicroelectronics |
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ST802RT1B 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 58 page ![]() Electrical specifications and timings ST802RT1A, ST802RT1B 50/58 Doc ID 17049 Rev 1 Symbol Parameter Test conditions Min. Typ. Max. Unit XTAL conditions tX1d X1 duty cycle 45 50 55 % tX1f X1 frequency 25/50/125 MHz tX1t X1 tolerance 50 ppm tX1CL X1 load capacitance 18 pF 10Base-T normal link pulse (NLP) Tnps NLP start after reset 10 Mbps 16 ms Tnpw NLP width 10 Mbps 100 ns Tnpc NLP period 10 Mbps 8 24 ms Fast link pulse (FLP) AC timing specification Number of pulses in one burst 17 33 Tflpw FLP width 100,00 ns Tflcpp Clock pulse to clock pulse period 111 125 139 µs Tflcpd Clock pulse to data pulse period 55,5 62,5 69,5 µs Tflbw Burst width 2 ms Tflbp FLP burst period 8 16 24 ms Trlat Receive latency - RXDV asserted after valid data on RXP/RXN MII- 100 Mb/s 160 ns Ttlat Transmit latency - data on TXP/TXN after TXEN asserted MII- 100 Mb/s 130 ns MII Management Interface AC timing specification Tmihl MDC clock high & low time 160 ns Tmip MDC clock period 400 ns Tmis MDIO setup time STA sources MDIO 10 ns Tmih MDIO hold time STA sources MDIO 10 ns Tmidco MDIO clock to output delay PHY sources MDIO 0 300 ns Table 35. General DC specification (continued) |
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