ST802RT1B datasheet(46/58 Pages) STMICROELECTRONICS

46 / 58 page

Device operation

ST802RT1A, ST802RT1B

46/58

Doc ID 17049 Rev 1

These two signals can be either driven by standard CMOS levels or by PECL levels. The

data coming from the optical transceiver are PECL signals and need to be converted to

CMOS level before being delivered to the data and clock recovery and then to the serial-to-

parallel interface to be transmitted to the digital portion.

7.20

PECL transmitter

This circuit is designed to acquire the data coming from the parallel-to-serial interface and

NRZ-to-NRZI converter, and to transmit it to the optical transceiver. In this case, the data is

received by the transmitter in a CMOS format and is transmitted to the optical portion in a

PECL format. See Figure 8 for the definition of PECL levels.

Table 32.

Configuration of signal detect voltage levels

SDn

SDp

Mode

Ground

TX mode

Ground

Positive voltage

Undefined state

Voltage>0.6

Undefined state

PECLLOW(PECLMID)

PECLLOW

FX mode asserted, but no data valid on the line

PECLHIGH(PECLMID)

PECLLOW

FX mode asserted, but no data valid on the line

PECLHIGH

Undefined state

PECLLOW(PECLMID)

PECLHIGH

FX mode asserted, link OK and data valid

Figure 8.

PECL levels

ST802RT1B 数据表(PDF) 46 Page - STMicroelectronics

ST802RT1B 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表下载

链接网址

ST802RT1B 数据表(PDF) 46 Page - STMicroelectronics

ST802RT1B 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

数据表 下载

链接网址

数据表下载