STW82102B datasheet(26/67 Pages) STMICROELECTRONICS

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General description

STW82102B

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Doc ID 018516 Rev 2

8.1.6

Lock detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD

signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is

high when the PLL is locked. The Lock Detector consumes current only during PLL

transients.

8.1.7

Mute until lock

This (software controlled) function shuts down the following elements until the PLL achieves

the lock status:

●

RF output stage

●

LO output buffer

●

mixer

●

IF amplifier circuitry

Under this setting there is no signal at the IF output stage or the LO output during a

frequency jump.

8.1.8

Charge pump

This block drives two matched current sources, Iup and Idown, which are controlled

respectively by the UP and DOWN PFD outputs. The nominal value of the output current is

controlled by an external resistor (to be connected to the REXT input pin) and the selection

of one of 8 possible values by a 3-bit word.

The minimum value of the output current is: IMIN = 2*VBG/REXT_CP (VBG~1.17 V)

Note:

The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are

forced to VDD/2.

Table 10.

Current values for CPSEL[2:0] selection

CPSEL2

CPSEL1

CPSEL0

Current

Value for REXT=4.7 k

000

IMIN

0.5 mA

001

2*IMIN

1.00 mA

010

3*IMIN

1.50 mA

011

4*IMIN

2.00 mA

100

5*IMIN

2.50 mA

101

6*IMIN

3.00 mA

110

7*IMIN

3.50 mA

111

8*IMIN

4.00 mA

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