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STW82102B 数据表(PDF) 41 Page - STMicroelectronics |
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STW82102B 数据表(HTML) 41 Page - STMicroelectronics |
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41 / 67 page  STW82102B I2C bus interface Doc ID 018516 Rev 2 41/67 CONTROL PLL control register Address: 0x04 Type: W Reset: 0x00 Description: Least significant bits of the reference clock divider ratio value and PLL control bits. 7 654 3210 [R1:0] PLL_A[1:0] CPSEL[2:0] PSC_SEL WW WW [7:6] R[1:0]: Reference clock divider ratio (bits R[9:2] in the REF_DIVIDER register) [5:4] PLL_A[1:0]: VCO amplitude [3:1] CPSEL[2:0]: Charge Pump output current [0] PSC_SEL: Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19) The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula : where DR equals 0.5 (VCOs output frequency divided by 2) and P is the selected Prescaler Modulus F LO D R BP A + ⋅ () F ref R ---------- ⋅⋅ = |
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