WM8946ECSSLASHR datasheet(78/175 Pages) WOLFSON

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WM8946

Production Data

PD, July 2012, Rev 4.3

Figure 32 WM8946 Clocking Overview

SYSCLK may be derived either from MCLK or from the FLL; this is selected using the SYSCLK_SRC

divider configured by SYSCLK_DIV. It is important that SYSCLK_DIV is correctly set in order to

produce 512 x fs at its output, where fs is the audio sampling rate.

The sampling rate for the CODEC and Digital Audio Interface is configured using the SR register field.

In Master mode, the frequency of the Left/Right Clock output on the LRCLK pin is the BCLK

frequency divided by 64 producing 32 BCLK cycles per channel. In Master mode, the BCLK_DIV

The WM8946 can output a configurable clock on the GPIO pins; this is enabled automatically

whenever a GPIO pin is configured for CLKOUT output. The source can either be before or after the

SYSCLK divider, as shown in Figure 32. The source is selected using CLKOUT_SEL, and may be

modified using a programmable divider configured by CLKOUT_DIV.

The WM8946 free-running oscillator required for GPIO input de-bounce and Interrupt functions must

be enabled using OSC_CLK_ENA whenever any of these functions is required.

The zero-cross facility on input and output PGAs requires a timeout clock. This is enabled using the

TOCLK_ENA bit. The oscillator must also be enabled using OSC_CLK_ENA.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clock Gen

control

OSC_CLK_ENA

Oscillator Enable

0 = Disabled

1 = Enabled

This needs to be set when a timeout

clock is required for PGA zero cross

or GPIO input detection

14:13

MCLK_PULL

[1:0]

MCLK pull-up / pull-down Enable

00 = no pull-up or pull-down

01 = pull-down

10 = pull-up

11 = reserved

CLKOUT_SEL

CLKOUT Source Select

0 = SYSCLK

1 = FLL or MCLK (set by

SYSCLK_SRC register)

WM8946ECS/R 数据表(PDF) 78 Page - Wolfson Microelectronics plc

WM8946ECS/R 数据表(HTML) 78 Page - Wolfson Microelectronics plc

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