WM8946ECSSLASHR datasheet(82/175 Pages) WOLFSON

82 / 175 page

WM8946

Production Data

PD, July 2012, Rev 4.3

For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations

yield an integer value of N.K, then it is recommended to adjust FLL_FRATIO in order to obtain a non-

integer value of N.K. Care must always be taken to ensure that the FLL operating frequency, FVCO, is

within its recommended limits of 90-100 MHz.

The register fields that control the FLL are described in Table 55. Example settings for a variety of

reference frequencies and output frequencies are shown in Table 56.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

FLL Control 1

12:11

FLL_CLK_RE

F_DIV [1:0]

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK must be divided down to

<=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

10:8

FLL_OUTDIV

[2:0]

001

FOUT clock divider

000 = 2

001 = 4

010 = 8

011 = 16

100 = 32

101 = 64

110 = 128

111 = 256

(FOUT = FVCO / FLL_OUTDIV)

7:5

FLL_CTRL_R

ATE [2:0]

000

Frequency of the FLL control block

000 = FVCO / 1 (Recommended value)

001 = FVCO / 2

010 = FVCO / 3

011 = FVCO / 4

100 = FVCO / 5

101 = FVCO / 6

110 = FVCO / 7

111 = FVCO / 8

Recommended that this register is not

changed from default.

4:2

FLL_FRATIO

[2:0]

000

FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

000 recommended for FREF > 1MHz

100 recommended for FREF < 16kHz

011 recommended for all other cases

WM8946ECS/R 数据表(PDF) 82 Page - Wolfson Microelectronics plc

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