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WM8948ECS/R 数据表(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8948ECS/R 数据表(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 189 page  WM8948 Production Data w PD, May 2011, Rev 4.1 40 The SE2 ‘enable’ bits are described in Table 14. Note that control fields must also be determined and written to the WM8948 using WISCE™ or other tools. The registers described below only allow the sub-blocks of SE2 to be enabled or disabled. Note that it is not recommended to access these control fields unless appropriate values have been written to the associated bits in registers R99 to R175. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R100 (64h) SE2_RETUNE _CONFIG 1 SE2_RETUNE_ R_ENA 0 SE2 Right channel ReTune™ filter enable 0 = Disabled 1 = Enabled 0 SE2_RETUNE_ L_ENA 0 SE2 Left channel ReTune™ filter enable 0 = Disabled 1 = Enabled R133 (85h) SE2_5BEQ_C ONFIG 0 SE2_5BEQ_L_ ENA 0 SE2 Left channel 5-band EQ enable 0 = Disabled 1 = Enabled Table 14 Signal Enhancement Block 2 (SE2) The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control (DRC)” section. |
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