WM8948ECSSLASHR datasheet(76/189 Pages) WOLFSON

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WM8948

Production Data

PD, May 2011, Rev 4.1

A-law Companding

100

120

0.2

0.4

0.6

0.8

Normalised Input

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Figure 30 A-Law Companding

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for

μ-law, all even data bits are inverted for A-law). Companded data is transmitted in the first

8 MSBs of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4

bits), as shown in Table 47.

BIT7

BIT[6:4]

BIT[3:0]

SIGN

EXPONENT

MANTISSA

Table 47 8-bit Companded Word Composition

8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows

samples to be passed using as few as 8 BCLK cycles per Left/Right Clock frame. When using DSP

mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles.

8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or

ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0.

LOOPBACK

A loopback function is provided for test and evaluation purposes. When the LOOPBACK register bit

is set, the DAC input data is fed through the DSP Core to the ADC output, as illustrated in Figure 31.

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