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WM8948ECS/R 数据表(PDF) 71 Page - Wolfson Microelectronics plc |
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WM8948ECS/R 数据表(HTML) 71 Page - Wolfson Microelectronics plc |
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71 / 189 page  Production Data WM8948 w PD, May 2011, Rev 4.1 71 In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an external master. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R6 (06h) Clock Gen control 3:1 BCLK_DIV [2:0] 011 BCLK Frequency (Master mode) 000 = SYSCLK 001 = SYSCLK / 2 010 = SYSCLK / 4 011 = SYSCLK / 8 100 = SYSCLK / 16 101 = SYSCLK / 32 110 = reserved 111 = reserved 0 MSTR 0 Digital Audio Interface Mode select 0 = Slave mode 1 = Master mode Table 44 Digital Audio Interface Control AUDIO DATA FORMATS Three basic audio data formats are supported: • Left justified • I2S • DSP mode All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information. PCM operation is supported using the DSP mode. The WM8948 can control the channel selection between the ADCs and the ADCDAT pin. Similarly, the channel selection between the DACDAT pin and the DACs is selectable. Digital inversion of the ADC or DAC data is also possible. The register bits controlling audio data format and channel configuration are described in Table 45. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Audio Interface 9 ADCR_SRC 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 8 ADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 7 DACR_SRC 1 Right DAC Data Source Select 0 = Right DAC outputs left interface data 1 = Right DAC outputs right interface data 6 DACL_SRC 0 Left DAC Data Source Select 0 = Left DAC outputs left interface data 1 = Left DAC outputs right interface data |
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