WM8948ECSSLASHR datasheet(30/189 Pages) WOLFSON

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WM8948

Production Data

PD, May 2011, Rev 4.1

Figure 12 Digital Microphone Interface Timing

The digital microphone interface control fields are described in Table 6.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management 1

DMIC_ENA

Enables Digital Microphone mode

0 = Audio DSP input is from ADC

1 = Audio DSP input is from digital

microphone interface

When DMIC_ENA = 0, the Digital

microphone clock (DMICCLK) is

held low.

Table 6 Digital Microphone Interface Control

ANALOGUE-TO-DIGITAL CONVERTER (ADC)

The WM8948 uses two 24-bit sigma-delta ADCs. The use of multi-bit feedback and high

oversampling rates reduces the effects of jitter and high frequency noise. The ADC full-scale input

level is proportional to LDOVOUT. See “Electrical Characteristics” section for further details. Any

input signal greater than full scale may overload the ADC and cause distortion.

The ADCs and associated digital record filters are enabled by the ADCL_ENA and ADCR_ENA

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management

ADCR_ENA

Right ADC Enable

0 = Disabled

1 = Enabled

ADCR_ENA must be set to 1 when

processing right channel data from

the ADC or Digital Microphone.

ADCL_ENA

Left ADC Enable

0 = Disabled

1 = Enabled

ADCL_ENA must be set to 1 when

processing left channel data from

the ADC or Digital Microphone.

Table 7 ADC Enable Control

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