WM8980CGEFLSLASHV datasheet(85/123 Pages) WOLFSON

85 / 123 page

Pre-Production

WM8980

PP, Rev 3.8, May 2012

Note that the GPIOPOL bits are not relevant for jack detection, it is the signal detected at the pin

which is used.

The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3

and OUT4 has 2 associated enables. OUT1_EN_0, OUT2_EN_0, OUT3_EN_0 and OUT4_EN_0 are

the output enable signal which are used if the selected jack detection pin is at logic 0 (after de-

bounce). OUT1_EN_1, OUT2_EN_1, OUT3_EN_1 and OUT4_EN_1 are the output enable signals

which are used if the selected jack detection pin is at logic 1 (after de-bounce).

Similar to the output enables, VMID, which can be driven out of OUT3 can be configured to be on/off

depending on the jack detection input polarity using the VMID_EN_0 and VMID_EN_1 bits.

The jack detection enables work as follows:

All OUT_EN signals have an AND function performed with their normal enable signals (in Table 50).

When an output is normally enabled at per Table 50, the selected jack detection enable (controlled

by selected jack detection pin polarity) is set 0, it will turn the output off. If the normal enable signal is

already OFF (0), the jack detection signal will have no effect due on the AND function.

During jack detection if the user desires an output to be un-changed whether the jack is in or not,

both the JD_EN settings i.e. JD_EN0 and JD_EN1, should be set to 0000.

The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the

VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should

set to 0 for all JD_EN0 or JD_EN1 settings.

If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs

to be controlled as normal via the normal output enables found in Table 50. Similarly the VMID_EN

signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

GPIO Control

5:4

JD_SEL

Pin selected as jack detection input

00 = GPIO1

01 = GPIO2

10 = GPIO3

11 = GPIO4

JD_EN

Jack Detection Enable

0=disabled

1=enabled

8:7

JD_VMID

[7] VMID_EN_0

[8] VMID_EN_1

R13

GPW Control

3:0

JD_EN0

Output enabled when selected jack

detection input is logic 0.

[0]= OUT1_EN_0

[1]= OUT2_EN_0

[2]= OUT3_EN_0

[3]= OUT4_EN_0

7:4

JD_EN1

Output enabled when selected jack

detection input is logic 1

[4]= OUT1_EN_1

[5]= OUT2_EN_1

[6]= OUT3_EN_1

[7]= OUT4_EN_1

Table 64 Jack Detect Register Control Bits

WM8980CGEFL/V 数据表(PDF) 85 Page - Wolfson Microelectronics plc

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