STM32F207IE datasheet(28/177 Pages) STMICROELECTRONICS

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Description

STM32F20xxx

28/177

Doc ID 15818 Rev 9

output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured

general-purpose timers.

They can also be used as simple time bases.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be

used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes.

The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

downcounter. It features:

●

A 24-bit downcounter

●

Autoreload capability

●

Maskable system interrupt generation when the counter reaches 0

●

Programmable clock source

2.2.21

Inter-integrated circuit interface (I²C)

Up to three I2C bus interfaces can operate in multimaster and slave modes. They can

support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the

7-bit dual addressing mode (as slave). A hardware CRC generation/verification is

embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.2.22

Universal synchronous/asynchronous receiver transmitters

(UARTs/USARTs)

The STM32F20x devices embed four universal synchronous/asynchronous receiver

transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous

receiver transmitters (UART4 and UART5).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to

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