STM32F207IE datasheet(32/177 Pages) STMICROELECTRONICS

32 / 177 page

Description

STM32F20xxx

32/177

Doc ID 15818 Rev 9

2.2.30

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S application. It allows to

achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S sample rate change without

disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 kHz to 192 kHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S

flow with an external PLL (or Codec output).

2.2.31

Digital camera interface (DCMI)

The camera interface is not available in STM32F205xx devices.

STM32F207xx products embed a camera interface that can connect with camera modules

and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The

camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It

features:

●

Programmable polarity for the input pixel clock and synchronization signals

●

Parallel data communication can be 8-, 10-, 12- or 14-bit

●

Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

●

Supports continuous mode or snapshot (a single frame) mode

●

Capability to automatically crop the image

2.2.32

True random number generator (RNG)

All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers

produced by an integrated analog circuit.

STM32F207IE 数据表(PDF) 32 Page - STMicroelectronics

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