数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADMP441 数据表(PDF) 4 Page - Analog Devices

部件名 ADMP441
功能描述  Omnidirectional Microphone with Bottom Port and I2S Digital Output
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADMP441 数据表(HTML) 4 Page - Analog Devices

  ADMP441 Datasheet HTML 1Page - Analog Devices ADMP441 Datasheet HTML 2Page - Analog Devices ADMP441 Datasheet HTML 3Page - Analog Devices ADMP441 Datasheet HTML 4Page - Analog Devices ADMP441 Datasheet HTML 5Page - Analog Devices ADMP441 Datasheet HTML 6Page - Analog Devices ADMP441 Datasheet HTML 7Page - Analog Devices ADMP441 Datasheet HTML 8Page - Analog Devices ADMP441 Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 16 page
background image
ADMP441
Data Sheet
Rev. B | Page 4 of 16
I²S DIGITAL INPUT/OUTPUT
–40°C < TA < +85°C, 1.8 V < VDD < 3.3 V, unless otherwise noted.
Table 2.
Limit1
Parameter
Symbol
Test Conditions/Comments
Min
Max
Unit
DIGITAL INPUT
Voltage Input Low (L/R, WS, SCK)
V
IL
0
0.25 × VDD
V
Voltage Input High (L/R, WS, SCK)
V
IH
0.7 × V
DD
V
DD
V
SD DIGITAL OUTPUT
Voltage Output Low
V
OL
V
DD = 1.8 V, ISINK = 0.25 mA
0.1 × V
DD
V
Voltage Output Low
V
OL
V
DD = 1.8 V, ISINK = 0.7 mA
0.3 × V
DD
V
Voltage Output High
V
OH
V
DD = 1.8 V, ISINK = 0.7 mA
0.7 × V
DD
V
Voltage Output High
V
OH
V
DD = 1.8 V, ISINK = 0.25 mA
0.9 × V
DD
V
Voltage Output Low
V
OL
V
DD = 3.3 V, ISINK = 0.5 mA
0.1 × V
DD
V
Voltage Output Low
V
OL
V
DD = 3.3 V, ISINK = 1.7 mA
0.3 × V
DD
V
Voltage Output High
V
OH
V
DD = 3.3 V, ISINK = 1.7 mA
0.7 × V
DD
V
Voltage Output High
V
OH
V
DD = 3.3 V, ISINK = 0.5 mA
0.9 × V
DD
V
1 Limits based on characterization results; not production tested.
Table 3. Serial Data Port Timing Specifications
Parameter
Description
Min
Max
Unit
t
SCH
SCK high
50
ns
t
SCL
SCK low
50
ns
t
SCP
SCK period
312
ns
f
SCK
SCK frequency
0.5
3.2
MHz
t
WSS
WS setup
0
ns
t
WSH
WS hold
20
ns
f
WS
WS frequency
7.8
49.3
kHz
TIMING DIAGRAM
SCK
WS
SD
tSCP
tSCH
tSCL
tWSH
tWSS
Figure 3. Serial Data Port Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com