Data Sheet

ADMP441

Rev. B | Page 9 of 16

SYSTEM MASTER

(DSP, MICROCONTROLLER,

CODEC)

CHIPEN

SCK

WS

L/R

SD

LEFT

ADMP441

GND GND GND

0.1µF

FROM VOLTAGE

REGULATOR

(1.8V TO 3.3V)

CHIPEN

SCK

WS

L/R

SD

RIGHT

ADMP441

GND GND GND

0.1µF

100kΩ

Figure 9. System Block Diagram

MSB

LSB

LEFT CHANNEL

MSB

LSB

RIGHT CHANNEL

HIGH-Z

HIGH-Z

HIGH-Z

1

2

3

4

24

25

26

32

33

34

35

36

56

57

58

64

WS

SCK (64 ×

SD (24-BIT)

Figure 10. Stereo Output I²S Format

MSB

LSB

LEFT CHANNEL

HIGH-Z

HIGH-Z

1

2

3

4

24

25

26

32

33

34

35

36

56

57

58

64

WS

SCK (64 ×

SD (24-BIT)

Figure 11. Mono Output I²S Format Left Channel (L/R = 0)

MSB

LSB

RIGHT CHANNEL

HIGH-Z

HIGH-Z

1

2

3

4

24

25

26

32

33

34

35

36

56

57

58

64

WS

SCK (64 ×

SD (24-BIT)

Figure 12. Mono Output I²S Format Right Channel (L/R = 1)