ADMP441

Data Sheet

Rev. B | Page 8 of 16

THEORY OF OPERATION

The ADMP441 is a high performance, low power, digital

output, omnidirectional MEMS microphone with a bottom

port. The complete ADMP441 solution consists of a MEMS

sensor, signal conditioning, an analog-to-digital converter, anti-

aliasing filters, power management, and an industry standard

24-bit I²S interface.

The ADMP441 complies with the TIA-920 Telecommunications

Telephone Terminal Equipment Transmission Requirements for

Wideband Digital Wireline Telephones standard.

UNDERSTANDING SENSITIVITY

The casual user of digital microphones may have difficulty

understanding the sensitivity specification. Unlike an analog

microphone (whose specification is easily confirmed with an

oscilloscope), the digital microphone output has no obvious

unit of measure.

The ADMP441 has a nominal sensitivity of −26 dBFS at 1 kHz

with an applied sound pressure level of 94 dB. The units are in

decibels referred to full scale. The ADMP441 default full-scale

acoustic tone at 1 kHz having a 1 Pa rms amplitude results in an

output digital signal whose peak amplitude is 420,426.

Although the industry uses a standard specification of 94 dB

SPL, the ADMP441 test method applies a 104 dB SPL signal.

The higher sound pressure level reduces noise and improves

repeatability. The ADMP441 has excellent gain linearity, and

the sensitivity test result at 94 dB is derived with very high

confidence from the test data.

POWER MANAGEMENT

The ADMP441 has three different power states: normal

operation, standby mode, and power-down mode.

Normal Operation

with SCK at 3.072 MHz) after initial power-up. The CHIPEN

pin then controls the power modes. The part is in normal opera-

tion mode when SCK is active and the CHIPEN pin is high.

Standby Mode

The microphone enters standby mode when the serial data

clock SCK stops and CHIPEN is high. Normal operation

SCK restarts.

The ADMP441 should not be transitioned from standby to

power-down mode, or vice versa. Standby mode is only

intended to be entered from the normal operation state.

Power-Down Mode

The microphone enters power-down mode when CHIPEN is

low, regardless of the SCK operation. Normal mode operation

after CHIPEN returns high while SCK is active.

is applied.

It is not recommended to supply active clocks (WS and SCK) to

this continuously turns on ESD protection diodes, which may

affect long-term reliability of the microphone.

STARTUP

cycles (85 ms with SCK at 3.072 MHz) following power-up.

I²S DATA INTERFACE

The slave serial data port’s format is I²S, 24-bit, twos comple-

ment. There must be 64 SCK cycles in each WS stereo frame, or

32 SCK cycles per data-word. The L/R control pin determines

whether the ADMP441 outputs data in the left or right channel.

For a stereo application, the SD pins of the left and right

ADMP441 microphones should be tied together as shown in

Figure 9. The format of a stereo I²S data stream is shown in

Figure 10. Figure 11 and Figure 12 show the formats of a mono

microphone data stream for left and right microphones,

respectively.

Data Output Mode

The output data pin (SD) is tristated when it is not actively

driving I²S output data. SD immediately tristates after the LSB

is output so that another microphone can drive the common

data line.

The SD trace should have a pull-down resistor to discharge the

line during the time that all microphones on the bus have

tristated their outputs. A 100 kΩ resistor is sufficient for this, as

shown in Figure 9.

Data-Word Length

The output data-word length is 24 bits per channel. The

ADMP441 must always have 64 clock cycles for every stereo

Data-Word Format

The default data format is I²S (twos complement), MSB-first. In

this format, the MSB of each word is delayed by one SCK cycle

from the start of each half-frame.