ADMP441

Data Sheet

Rev. B | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

4

L/R

6 GND

3

WS

2

SD

8 CHIPEN

1

SCK

9 GND

BOTTOM VIEW

(Not to Scale)

ADMP441

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1

SCK

Input

Serial Data Clock for I²S Interface.

2

SD

Output

Serial Data Output for I²S Interface. This pin tristates when not actively driving the appropriate

output channel. The SD trace should have a 100 kΩ pull-down resistor to discharge the line during

the time that all microphones on the bus have tristated their outputs.

3

WS

Input

Serial Data-Word Select for I²S Interface.

4

L/R

Input

Left/Right Channel Select. When set low, the microphone outputs its signal in the left channel of

the I²S frame; when set high, the microphone outputs its signal in the right channel.

5

GND

Ground

Ground. Connect to ground on the PCB.

6

GND

Ground

Ground. Connect to ground on the PCB.

7

V

DD

Power

Power, 1.8 to 3.3 V. This pin should be decoupled to Pin 6 with a 0.1 μF capacitor.

8

CHIPEN

Input

Microphone Enable. When set low (ground), the microphone is disabled and put in power-down

mode. When set high (V

9

GND

Ground

Ground. Connect to ground on the PCB.