41594B datasheet(109/372 Pages) MICROCHIP

109 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 109

PIC12LF1840T48A

12.0 I/O PORTS

In general, when a peripheral is enabled, that pin may

not be used as a general purpose I/O pin.

The port has three registers for its operation. These

registers are:

• TRISA register (data direction register)

• PORTA register (reads the levels on the pins of

the device)

• LATA register (output latch)

PORTA has the following additional registers. They

are:

• ANSELA (analog select)

• WPUA (weak pull-up)

The Data Latch (LATA register) is useful for

read-modify-write operations on the value that the I/O

pins are driving.

A write operation to the LATA register has the same

affect as a write to the corresponding PORTA register.

A read of the LATA register reads of the values held in

the I/O port latches, while a read of the PORTA register

reads the actual I/O pin value.

The port has analog functions and has an ANSELA

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 12-1.

FIGURE 12-1:

GENERIC I/O PORT

OPERATION

12.1

Alternate Pin Function

The Alternate Pin Function Control (APFCON) register

is used to steer specific peripheral input and output

functions between different pins. The APFCON register

is shown in Register 12-1. For this device family, the

following functions can be moved between different

pins.

•RX/DT

•TX/CK

•SDO

•SS (Slave Select)

•T1G

•P1B

• CCP1/P1A

These bits have no effect on the values of any TRIS

correct pin. The unselected pin will be unaffected.

Write LATA

Data Register

I/O pin

Read PORTA

Write PORTA

TRISA

Read LATA

Data Bus

To peripherals

ANSELA

VDD

VSS

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