REV. 0

–14–

AD5232

Table X. Active Trimming of One POT Followed by a Save to

Nonvolatile Memory (PCB Calibrate)

SDI

SDO

Action

Wiper W1 moves to 1/4 full-scale

position.

Increments RDAC1 register by one to

segment away from terminal B.

Increments RDAC1 register by one to

resistor segment away from terminal B.

Continue until desired wiper position

reached.

Saves RDAC1 register data into

corresponding nonvolatile EEMEM1

EQUIPMENT CUSTOMER STARTUP SEQUENCE FOR A

PCB CALIBRATED UNIT WITH PROTECTED SETTINGS

PCB setting: Tie

WP to GND [prevents changes in PCB

wiper set position]

Optional: Strobe

PR pin [ensures full power ON preset of

wiper register with EEMEM contents in unpredictable supply

sequencing environments]

Table XI. Using Left Shift by One to Change Circuit Gain in

6 dB Steps

SDI

SDO

Action

Moves Wiper W2 to double the present

data value contained in RDAC2 regis-

ter, in the direction of the A terminal.

Moves Wiper W2 to double the present

data value contained in RDAC2 regis-

ter, in the direction of the A terminal.

Table XII. Storing Additional Data in Nonvolatile Memory

SDI

SDO

Action

location USER1.

location USER2.

Table XIII. Reading Back Data from Various Memory Locations

SDI

SDO

Action

Prepares data read from USER3 location.

Assumption: USER3 previously loaded

NOP instruction #0 sends 16-bit word

out of SDO where the last 8 bits con-

tain the contents of USER3 location.

NOP command ensures device returns

to idle power dissipation state.

Analog Devices offers the AD5232EVAL board for sale to

simplify evaluation of these programmable devices controlled by

a personal computer via the printer port.

TEST CIRCUITS

Figures 13 to 22 define the test conditions used in the product

specification’s table.

A

W

B

NC

DUT

NC = NO CONNECT

Figure 13. Resistor Position Nonlinearity Error (Rheostat

Operation; R-INL, R-DNL)

A

W

B

DUT

V+

Figure 14. Potentiometer Divider Nonlinearity Error Test

Circuit (INL, DNL)

A

W

B

DUT

Figure 15. Wiper Resistance Test Circuit

A

W

B

10%

PSRR (dB) = 20 LOG

(

)

~

PSS (%/%) =

V+

Figure 16. Power Supply Sensitivity Test Circuit (PSS, PSRR)

~

OFFSET BIAS

OFFSET

GND

AB

DUT

W

5V

OP279

Figure 17. Inverting Gain Test Circuit