REV. 0

AD5232

–15–

~

OFFSET BIAS

OFFSET

GND

AB

DUT

W

5V

OP279

Figure 18. Noninverting Gain Test Circuit

~

OFFSET

GND

A

B

DUT

W

+15V

OP42

–15V

2.5V

Figure 19. Gain vs. Frequency Test Circuit

+

_

DUT

0.1V

0.1V

W

B

Figure 20. Incremental ON Resistance Test Circuit

DUT

W

B

NC

NC

GND

A

NC = NO CONNECT

Figure 21. Common-Mode Leakage Current Test Circuit

W2

B2

A2

~

NC

W1

A1

Figure 22. Analog Crosstalk Test Circuit

Flash/EEMEM Reliability

The Flash/EE Memory array on the AD5232 is fully qualified

for two key Flash/EE memory characteristics, namely Flash/EE

Memory Cycling Endurance and Flash/EE Memory Data

Retention.

Endurance quantifies the ability of the Flash/EE memory to be

cycled through many Program, Read, and Erase cycles. In real

terms, a single endurance cycle is composed of four indepen-

dent, sequential events. These events are defined as:

a. Initial page erase sequence

b. Read/verify sequence

c. Byte program sequence

d. Second read/verify sequence

During reliability qualification Flash/EE memory is cycled from

limit of the on-chip Flash/EE memory.

As indicated in the specification pages of this data sheet, the

AD5232 Flash/EE Memory Endurance qualification has been

carried out in accordance with JEDEC Specification A117 over

the industrial temperature range of –40

°C to +85°C. The results

allow the specification of a minimum endurance figure over supply

and temperature of 100,000 cycles, with an endurance figure of

700,000 cycles being typical of operation at 25

°C.

Retention quantifies the ability of the Flash/EE memory to retain

its programmed data over time. Again, the AD5232 has been

qualified in accordance with the formal JEDEC Retention Life-

time Specification (A117) at a specific junction temperature

memory is cycled to its specified endurance limit described above,

before data retention is characterized. This means that the Flash/EE

memory is guaranteed to retain its data for its full-specified reten-

tion lifetime every time the Flash/EE memory is reprogrammed. It

should also be noted that retention lifetime, based on an activa-

300

250

0

40

200

150

100

50

50

60

70

80

90

100

110

ADI TYPICAL

PERFORMANCE

AT

Figure 23. Flash/EE Memory Data Retention