AD5231 datasheet(3/20 Pages) AD

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–3–

REV. 0

nV/

√Hz

Parameter

Symbol

Conditions

Min

Typ

Max Unit

DYNAMIC CHARACTERISTICS

5, 9

Bandwidth

–3 dB, BW_10 k

Ω, R = 10 kΩ

500

kHz

Total Harmonic Distortion

THDW

VA = 1 V rms, VB = 0 V, f = 1 kHz,

RAB = 10 k

Ω

0.022

THDW

VA =1 V rms, VB = 0 V, f = 1 kHz,

RAB = 50 kΩ, 100 kΩ

0.045

VW Settling Time

VDD =5 V, VSS =0 V, VA = VDD, VB = 0 V,

VW = 0.50% Error Band, Code 00H to 80H

For RAB = 10 kΩ/50 kΩ/100 kΩ

0.65/3/6

µs

Resistor Noise Voltage

eN_WB

RWB = 5 k

Ω, f = 1 kHz

Crosstalk (CW1/CW2)CT

VA = VDD, VB = 0 V, Measure VW with

Adjacent VR Making Full-Scale Code Change

–5

nV-s

Analog Crosstalk (CW1/CW2)CTA

VA1 = VDD, VB1 = 0 V, Measure VW1

with VW2 = 5 V p-p @ f = 10 kHz,

Code1 = 80H; Code2 = FFH

–70

INTERFACE TIMING CHARACTERISTICS – Applies to All Parts

5, 10

Clock Cycle Time (tCYC)t1

CS Setup Time

CLK Shutdown Time to

CS Rise

1tCYC

Input Clock Pulsewidth

t 4 , t 5

Clock Level High or Low

Data Setup Time

From Positive CLK Transition

Data Hold Time

From Positive CLK Transition

CS to SDO-SPI Line Acquire

CS to SDO-SPI Line Release

t 9

CLK to SDO Propagation Delay

t10

RP = 2.2 k

Ω, C

L < 20 pF

CLK to SDO Data Hold Time

t11

RP = 2.2 k

Ω, C

L < 20 pF

CS High Pulsewidth12

t12

CS High to CS High12

t 13

4tCYC

RDY Rise to

CS Fall

t 14

0ns

CS Rise to RDY Fall Time

t 15

0.1

0.15

Read/Store to Nonvolatile EEMEM

t 16

Applies to Command 2H, 3H, 9H

CS Rise to Clock Rise/Fall Setup

t17

Preset Pulsewidth (Asynchronous)

tPRW

Not Shown in Timing Diagram

Preset Response Time to RDY High tPRESP

PR Pulsed Low to Refreshed

Wiper Positions

µs

FLASH/EE MEMORY RELIABILITY CHARACTERISTICS

Endurance

100

K Cycles

Data Retention

100

Years

NOTES

1Typical parameters represent average readings at 25

°C and V

DD = 5 V.

2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W ~ 50 µA @ VDD = 2.7 V and

IW ~ 400 µA @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 µA for the RAB = 50 kΩ and IW ~ 25 µA for the RAB = 100 kΩ version. See Figure 13.

3INL and DNL are measured at V

W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = VSS. DNL

specification limits of

± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.

4Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.

5Guaranteed by design and not subject to production test.

6Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of V

DD/2.

7Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.

DISS is calculated from (IDD

VDD) + (ISS

VSS).

9All dynamic characteristics use V

DD = +2.5 V and VSS = –2.5 V unless otherwise noted.

10See timing diagram for location of measured values. All input control voltages are specified with t

R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both V DD = 3 V or 5 V.

11Propagation delay depends on value of V

DD, RPULL_UP, and CL. See applications text.

12Valid for commands that do not activate the RDY pin.

13RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the

PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation

at TA = –40°C and VDD < 3 V extends the save time to 35 ms.

14Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V

DD = 2.7 V, TA = –40°C to +85°C, typical endurance at 25°C is

700,000 cycles.

15Retention lifetime equivalent at junction temperature (T

J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV

will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. The AD5232 contains 9,646

transistors. Die size: 69 mil

115 mil, 7,993 sq. mil.

Specifications subject to change without notice

AD5232

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