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AD7002AS 数据表(PDF) 7 Page - Analog Devices |
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AD7002AS 数据表(HTML) 7 Page - Analog Devices |
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7 / 16 page  AD7002 –7– REV. B RECEIVE SECTION TIMING1 Limit at Parameter TA = –40 C to +85 C Units Description t23 0 ns min Rx SLEEP Hold Time After CLK1, CLK2 High t24 25 ns min Rx SLEEP Setup Time Before CLK1, CLK2 High t25 0 ns min Rx SYNC to Rx SLEEP Asserted 2 39 t1 ns max RATE 0 15 t1 ns max RATE 1 t26 Rx CLK Active After CLK1 Rising Edge Following Falling Edge of Rx SLEEP 32 t1 + t2 ns MODE 0 31 t1 + t2 ns MODE 1 t27 Rx CLK Cycle Time 3 t1 ns MODE 0 2 t1 ns MODE 1 t28 Rx CLK High Pulse Width 25 ns min MODE 0 90 ns min MODE 1 t29 Rx CLK Low Pulse Width 25 ns min MODE 0 30 ns min MODE 1 t30 10 ns min Propagation Delay from CLK1, CLK2 High to Rx CLK High 30 ns max t31 20 ns min Rx SYNC Valid Prior to Rx CLK Falling t32 Rx SYNC High Pulse Width t1 ns MODE 0 2 t1 ns MODE 1 t33 Rx SYNC Cycle Time 3 24 t1 ns MODE 0 RATE 0 12 t1 ns MODE 0 RATE 1 48 t1 ns MODE 1 RATE 0 24 t1 ns MODE 1 RATE 1 t34 Rx DATA Valid After Rx CLK Rising Edge 5 ns max MODE 0 t1 + 5 ns max MODE 1 t35 5 ns max MODE 0 only, Propagation Delay from Rx CLK Rising Edge to I/ Q t36 10 ns typ Digital Output Rise Time 4 t37 10 ns typ Digital Output Fall Time 4 CALIBRATION AND CONTROL TIMING Limit at Parameter TA = –40 C to +85 C Units Description t38 25 ns min SLEEP to CAL Setup Time t39 608 t1 ns min CAL Pulse Width t40 25 ns min RATE, MODE or THREE-STATE ENABLE Setup Time NOTES 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2t 25 specifies a window, after Rx SYNC which marks the beginning of I data, that Rx SLEEP should be asserted for the subsequent IQ data pair to be last prior to entering SLEEP mode. 3See Figure 2 for test circuit. 4Digital output rise and fall times specify the time required for the output to go between 10% and 90% of 5 V. Specifications subject to change without notice. (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fCLK1 = fCLK2 = 13 MHz; TA = TMIN to TMAX, unless otherwise noted) (AVDD = +5 V 10%; DVDD = +5 V 10%; AGND = DGND = 0 V, fAUX CLK = 13 MHz; TA = TMIN to TMAX, unless otherwise noted) |
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