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AD7002AS 数据表(PDF) 13 Page - Analog Devices |
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AD7002AS 数据表(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() AD7002 –13– REV. B t 24 CLK1, CLK2 (I) Rx SLEEP1 (I) Rx SLEEP2 (I) Rx CLK (O) Rx SYNC (O) Rx DATA (O) t23 t28 t 29 t 30 t 32 t 31 t 34 t 33 t 35 t 35 NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT 26 27 tt I MSB I LSB Q MSB Q LSB I MSB I LSB Q MSB Q LSB 25 t I/Q (O) Figure 16. MODE 0 RATE 1 Receive Timing t 24 CLK1, CLK2 (I) Rx SLEEP1 (I) Rx SLEEP2 (I) Rx CLK (O) Rx SYNC (O) t26 Rx DATA (O) t23 t 27 t28 t 30 t 31 t 33 t35 t 35 t 29 I MSB I LSB Q MSB Q LSB t 34 I MSB t32 NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT I LSB Q MSB Q LSB t25 I/Q (O) Figure 17. MODE 0 RATE 0 Receive Timing t24 CLK1, CLK2 (I) Rx SLEEP1 (I) Rx SLEEP2 (I) Rx CLK (O) Rx SYNC (O) I DATA (O) Q DATA (O) t23 I MSB t29 I LSB t30 t 31 I MSB I LSB Q MSB Q LSB Q MSB Q LSB NOTE: (I) = DIGITAL INPUT; (O) = DIGITAL OUTPUT t 27 t28 t32 t 33 t 34 t 34 t25 t26 Figure 18. MODE 1 RATE 1 Receive Timing |
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