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AD7002AS 数据表(PDF) 16 Page - Analog Devices |
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AD7002AS 数据表(HTML) 16 Page - Analog Devices |
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16 / 16 page ![]() AD7002 –16– REV. B PQFP Pin Number Mnemonic Function 19 I/ Q (QDATA) This is a dual function digital output. When the device is operating in MODE 0, it indicates whether IDATA or QDATA is present on Rx DATA pin. In MODE 1, QDATA is available at this pin. 20 Rx SYNC Synchronization output for framing I and Q data at the receive interface. 21 Rx CLK Output clock for the receive section interface. 22 THREE-STATE This digital input controls the output three-state drivers on the receive section interface. When CONTROL it is High, the outputs are enabled. When Low, they are in high impedance. 23 CAL Calibration control pin for digital filter section. When brought high, for a minimum of 608 master clock cycles, the receive section enters a calibration cycle. Where I and Q offset registers are up- dated, when the CAL pin is brought low again, with offset values which are subtracted out from subsequent ADC conversions. CAL should remain Low during normal operation. 29 MZERO Digital control input. When high the analog modulator input is internally grounded (i.e., tied to VREF). MZERO, in conjunction with CAL, allows on-chip offsets to be calibrated out. Low for normal operation. 27, 24 Rx SLEEP1, Power-down control inputs for receive section. When high, the receive section goes into Rx SLEEP2 standby mode and draws minimal current. Rx SLEEP1 and Rx SLEEP2 must be externally hardwired together for normal device operation. AUXILIARY INTERFACE AND CONTROL 32 AUX LATCH Synchronization input for the auxiliary DACs’ shift register and AUX OUT. 31 AUX CLK Clock input for the auxiliary DACs’ 16-bit shift register. AUX DATA is latched on the falling edge of AUX CLK while AUX LATCH is low. 30 AUX DATA Data input for the AUX DACs and the AUX FLAG serial interface. 33 AUX FLAG Digital output flag, this can be used as a digital control output and is controlled from the auxiliary serial interface. TEST 8, 26 Test l, Test 2 Test pins for factory use only. These pins should be left unconnected and not used as routes for other circuit signals. 14, 43 Test 3, Test 4 Test pins. These must be tied to ground for normal device operation. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack Package (S-44) 1 44 34 33 23 22 12 11 TOP VIEW PIN 1 0.016 (0.41) 0.012 (0.30) 0.033 (0.84) 0.029 (0.74) 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) 0.398 (10.11) 0.390 (9.91) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) 0.398 (10.11) 0.390 (9.91) 0.548 (13.925) 0.546 (13.875) 8 ° 0.8 ° |
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