| 数据搜索系统,热门电子元器件搜索 |
|
AD7008/PCB 数据表(PDF) 14 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7008/PCB 数据表(HTML) 14 Page - Analog Devices |
|
14 / 16 page ![]() START 0 Hz RBW 3 kHz VBW 10 kHz STOP 25 000 000.0 Hz ST 5.6 SEC REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 4 500 000.0 Hz –54.7 dB Figure 29. fCLK = 50 MHz, fOUT = 9.1 MHz START 0 Hz RBW 3 kHz VBW 10 kHz STOP 25 000 000.0 Hz ST 5.6 SEC REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 11 100 000.0 Hz –54.1 dB CENTER 13 100 000.0 Hz RBW 3 kHz VBW 10 kHz SPAN 25 000 000.0 Hz ST 5.6 SEC REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 10 675 000.0 Hz –47.0 dB Figure 31. fCLK = 50 MHz, fOUT = 13.1 MHz Figure 30. fCLK = 50 MHz, fOUT = 11.1 MHz CENTER 16 500 000.0 Hz RBW 3 kHz VBW 10 kHz SPAN 25 000 000.0 Hz ST 5.6 SEC REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 500 000.0 Hz –44.8 dB 130 50 50 70 60 10 0 90 80 100 110 120 40 30 20 MASTER CLOCK – MHz Figure 32. fCLK = 50 MHz, fOUT = 16.5 MHz Figure 33. Typical Current Consumption vs. Frequency Figure 34. Typical Plot of SFDR vs. Master Clock Frequency When fOUT = 1/3fCLK, Frequency Word = 5671C71C Hex –40 –75 50 –60 –70 10 –65 0 –45 –55 –50 40 30 20 MASTER CLOCK – MHz REV. B –14– AD7008–Typical Performance Characteristics |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |