AD7008SLASHPCB datasheet(3/16 Pages) AD

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AD7008

REV. B

–3–

TIMING CHARACTERISTICS (V

AA = VDD +5 V

± 5%; T

A = TMIN to TMAX, unless otherwise noted)

AD7008AP20

AD7008JP50

Parameter

Min

Typ

Max

Min

Typ

Max

Units

Test Conditions/Comments

CLOCK Period

CLOCK High Duration

CLOCK Low Duration

CLOCK to Control Setup Time

CLOCK to Control Hold Time

4t1

LOAD Period

2t1

LOAD High Duration

LOAD High to TC0–TC3 Setup Time

LOAD High to TC0–TC3 Hold Time

t10

Falling to CS Low Setup Time

t11

Falling to CS Low Hold Time

t12

Minimum WR Low Duration

t13

Minimum WR High Duration

t14

to D0–D15 Setup Time

t15

to D0–D15 Hold Time

t16

SCLK Period

t17

SCLK High Duration

t18

SCLK Low Duration

t19

SCLK Rising to SDATA Setup Time

t20

SCLK Rising to SDATA Hold Time

NOTE

1May be reduced to 1t

1 if LOAD is synchronized to CLOCK and Setup (t 4) and Hold (t5) Times for LOAD to CLOCK are observed.

D0–D15

VALID DATA

t11

t10

t12

t13

t15

t14

Figure 3. Parallel Port Timing

SCLK

DB31

SDATA

DB0

Figure 4. Serial Port Timing

Figure 2. Register Transfer Timing

LOAD

TC0–TC3

VALID

CLOCK

FSEL, LOAD,

TC3–TC0

VALID

Figure 1. Clock Synchronization Timing

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