29

AN30183A

Ver. AEB

1

0

0

VL1[3:0]

VL2[3:0]

Name

DAC2

R/W

02h

1

0

0

0

0

Default

Bit

R/W

Register

Name

Sub

Address

D5

D6

D7

Data

D0

D1

D2

D3

D4

3.30

3.00

2.85

2.80

2.70

2.60

1.85

1.80

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00 (Default)

Output voltage

[V]

0

0

1

1

1

0

1

1

VL2[3:0]

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1

0

0

1

0

1

0

1

1

1

0

1

0

1

1

1

1

1

1

1

D4

D5

D6

D7

3.30

3.00

2.85

2.80

2.70

1.90

1.85 (Default)

1.80

1.70

1.60

1.50

1.40

1.30

1.20

1.10

1.00

Output voltage

[V]

0

0

1

1

1

0

1

1

VL1[3:0]

0

0

0

0

1

0

0

0

0

1

0

0

1

1

0

0

0

0

1

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

0

1

1

0

0

1

0

1

0

1

1

1

0

1

0

1

1

1

1

1

1

1

D0

D1

D2

D3

D7-4 : LDO2 Register for output voltage setup

D3-0 : LDO1 Register for output voltage setup

Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

OPERATION ( Continued )

3. Register map details