35

AN30183A

Ver. AEB

2.4 V

1.24 V

2.2 V

2.1 V

1.5 V

1.4 V

NM

PS

NM

NM

PS

NM

@ 150

μs

NM

PS

NM

VBAT

(External input signal)

REF

(IC output signal)

VREG

(IC output signal)

REGW

(IC inner signal)

DVDD

DET

(IC inner signal)

RESET

(External input signal)

LDO1ON

(External input signal)

VLDO1

(IC output signal)

VLDO

2/3/4

(IC output signal)

DCDC1

(IC output signal)

OSC

(IC inner signal)

DVDD

(External input signal)

I2C input

PS⇔NM

PS⇔NM

All registers are initialized

(LDO and DCDC are turned off)

LDO* stop is possible even in PS mode

LDO1 starts in NM mode

I2C acceptance starts

I2C acceptance stops

DVDD_DET:High and RESET:High

= I2C acceptance ON

DVDD_DET:Low and RESET:Low

= I2C acceptance OFF

at DCDC-start

at LDO-start

I2C input

I2C stops

Pin LDO1 stops

Pin LDO1 starts

I2C starts

I2C stops

I2C starts

I2C stops

I2C starts

Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

OPERATION ( Continued )

4. Timing Chart (Sequence – 1 (DVDD input externally))