AD9807/AD9805

–18–

REV. 0

discharging include the amount of time that input switch S1 is

turned on, the input impedance of the AD9807/AD9805 and

the output impedance of the circuit driving the coupling

may not necessarily occur over a continuous period of time; it may

actually be an accumulation of discrete charging periods. This

is typical where CDSCLK1 is asserted only during the reset

levels of the pixels. In this case, the quantity, m

× T, may be

CDSCLK1 is asserted and T is the period of the assertion.

Given these quantities, the maximum value for the input

coupling capacitor is computed from the equation:

/ln









calculated by taking the difference between the CCD’s reset

the level of accuracy to which the input capacitor must be charged

and is system dependent. Usually the allowable droop of the

capacitor voltage is taken into account. This is discussed below.

For example, if the CCD output can droop up to 1 volt without

affecting the accuracy of the CDS, then clamping to within

about one tenth of the allowable droop (100 mV) should be

sufficient in most cases.

voltage droop. It is important that the signals at the inputs of

the AD9807/AD9805 remain within the supply voltage limits so

the CDSs are able to accurately digitize the difference between

the reset level and the video level. Assuming the input voltages

are initially biased at the correct levels, the input bias current of

the AD9807/AD9805 inputs will discharge the input coupling

capacitors resulting in voltage droop. After taking into account

any droop, the peaks of the input signal must remain within the

required voltage limits of AD9807/AD9805 inputs.

droop, dV, in one scan line, the number of pixels across one scan

line, n, the period of one pixel, t, and the input bias current of

dV









× n × t

Some examples are given below showing the typical range of

capacitor values.

Example 1

A 5000 pixel CCD running at a 2 MHz (t = 500 ns) has a reset

level of 4.5 volts and an output voltage of 1.8 volts. The number

of optical black pixels available at the start of a line is 18. Using

the AD9807/AD9805 with an input span of 4 volts and a PGA

to 3 volts during the optical black pixels, the required voltage

and the maximum droop allowable during one line, dV, will be

(3 – 1.8) or 1.2 volts before the signal droops below 0 volts.

With dV = 1.2 volts, a clamp accuracy of 100 mV should be

amount of time available to charge up the input capacitor,

switch is closed) times the number of optical black pixels. With

a pixel rate of 2 MHz, CDSCLK1 would typically be around

1.8

µs. The input impedance of the AD9807 is 5K, and the

input bias current is 10 nA. Assume the source impedance

Note that a capacitor larger than 133 pF would still work, it

would just take several lines to charge the input capacitor up

clocking the CCD and CDSCLK1 while the transport motor

several hundred

µs or more, meaning that only very fine

adjustment would be needed during the limited number of

optical black pixels.

Example 2

A 7926 pixel CCD running at 2 MHz has a reset level of 6 volts,

an output voltage of 2.9 volts and 80 optical black pixels. Using

the AD9807 with an input span of 4 volts and a PGA gain of

× 100 ns or 8

µs, and V

Again, a larger capacitor may be used if several lines are allowed

for to initially charge up the cap, or if the CCD and CDSCLK1

are clocked during the moving of the scanner carriage.

Generating 3-Channel Timing from a 16

Master Clock

Generating the required signals for CDSCLK1, CDSCLK2 and

ADCCLK is easily accomplished with a master clock running

16

× the desired per channel pixel rate (i.e., 2 MSPS pixel rate

requires 32 MHz master clock). The timing diagram shown

in Figure 18 meets all the minimum and maximum timing

specifications. Note that a 16

× master clock using only rising

edges was chosen instead of using both edges of an 8

× rate

clock to ensure immunity to duty cycle variations.

MASTER

(32MHz)

CDSCLK1

CDSCLK2

ADCCLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

500ns

Figure 18. Timing Scheme Using 16

× Master Clock