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AD9849 数据表(PDF) 14 Page - Analog Devices |
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AD9849 数据表(HTML) 14 Page - Analog Devices |
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14 / 36 page ![]() REV. 0 AD9848/AD9849 –14– Bit Default Address Content Width Value Register Name Register Description CLPDM # Bits 146 64 [0] 1 01 clpdmdir CLPDM Internal/External (0 = Internal, 1 = External) 65 [0] 1 00 clpdmpol CLPDM External Active Polarity (0 = Low Active, 1 = High Active) 66 [0] 1 01 clpdmspol0 Sequence #0: Start Polarity for CLPDM 67 [5:0] 6 2C clpdmtog1_0[5:0] Sequence #0: Toggle Position 1 for CLPDM 68 [5:0] 6 00 clpdmtog1_0[11:6] 69 [5:0] 6 35 clpdmtog2_0[5:0] Sequence #0: Toggle Position 2 for CLPDM 6A [5:0] 6 00 clpdmtog2_0[11:6] 6B [0] 1 01 clpdmspol1 Sequence #1: Start Polarity for CLPDM 6C [5:0] 6 3E clpdmtog1_1[5:0] Sequence #1: Toggle Position 1 for CLPDM 6D [5:0] 6 02 clpdmtog1_1[11:6] 6E [5:0] 6 16 clpdmtog2_1[5:0] Sequence #1: Toggle Position 2 for CLPDM 6F [5:0] 6 03 clpdmtog2_1[11:6] 70 [0] 1 00 clpdmspol2 Sequence #2: Start Polarity for CLPDM 71 [5:0] 6 3F clpdmtog1_2[5:0] Sequence #2: Toggle Position 1 for CLPDM 72 [5:0] 6 3F clpdmtog1_2[11:6] 73 [5:0] 6 3F clpdmtog2_2[5:0] Sequence #2: Toggle Position 2 for CLPDM 74 [5:0] 6 3F clpdmtog2_2[11:6] 75 [0] 1 01 clpdmspol3 Sequence #3: Start Polarity for CLPDM 76 [5:0] 6 3F clpdmtog1_3[5:0] Sequence #3: Toggle Position 1 for CLPDM 77 [5:0] 6 3F clpdmtog1_3[11:6] 78 [5:0] 6 3F clpdmtog2_3[5:0] Sequence #3: Toggle Position 2 for CLPDM 79 [5:0] 6 3F clpdmtog2_3[11:6] 0 00 clpdmscp0 CLPDM Sequence-Change-Position #0 (Hardcoded to 0) 7A [1:0] 2 00 clpdmsptr0 CLPDM Sequence Pointer for SCP #0 7B [5:0] 6 3F clpdmscp1[5:0] CLPDM Sequence-Change-Position #1 7C [5:0] 6 3F clpdmscp1[11:6] 7D [1:0] 2 00 clpdmsptr1 CLPDM Sequence Pointer for SCP #1 7E [5:0] 6 3F clpdmscp2[5:0] CLPDM Sequence-Change-Position #2 7F [5:0] 6 3F clpdmscp2[11:6] 80 [1:0] 2 00 clpdmsptr2 CLPDM Sequence Pointer for SCP #2 81 [5:0] 6 3F clpdmscp3[5:0] CLPDM Sequence-Change-Position #3 82 [5:0] 6 3F clpdmscp3[11:6] 83 [1:0] 2 00 clpdmsptr3 CLPDM Sequence Pointer for SCP #3 |
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