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AD9849 数据表(PDF) 24 Page - Analog Devices |
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AD9849 数据表(HTML) 24 Page - Analog Devices |
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24 / 36 page ![]() REV. 0 AD9848/AD9849 –24– H-Counter Synchronization The H-Counter reset occurs on the sixth CLI rising edge fol- lowing the HD falling edge. The PxGA steering is synchronized with the reset of the internal H-Counter. (See Figure 13.) 000 1 1 2 111 0 0 3 11 00 01234 5 6 7 8 9 10 11 12 14 15 0 1 2 3 02 3 4 H-COUNTER RESET VD NOTES 1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE. 2. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN). 3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION. HD XX XX X X X PxGA GAIN REGISTER CLI XX XX X X X H-COUNTER (PIXEL COUNTER) 3ns MIN 23 5 3ns MIN X X Figure 13. H-Counter Synchronization |
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