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AD9849 数据表(PDF) 20 Page - Analog Devices

部件名 AD9849
功能描述  CCD Signal Processors with Integrated Timing Driver
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9849 数据表(HTML) 20 Page - Analog Devices

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REV. 0
AD9848/AD9849
–20–
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9848/
AD9849 features on-chip output drivers for the RG and H1–H4
outputs. These drivers are powerful enough to directly drive the
CCD inputs. The H-driver current can be adjusted for optimum
rise/fall time into a particular load by using the DRV registers. The
RG drive current is adjustable using the RGDRV register. Each
3-bit DRV register is adjustable in 3.5 mA increments, with the
minimum setting of 0 equal to OFF or three-state, and the maxi-
mum setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/
H3. The internal propagation delay resulting from the signal
inversion is less than l ns, which is significantly less than the
typical rise time driving the CCD load. This results in a H1/H2
crossover voltage at approximately 50% of the output swing.
The crossover voltage is not programmable.
Digital Data Outputs
The AD9848/AD9849 data output phase is programmable
using the DOUTPHASE register. Any edge from 0 to 47 may
be programmed, as shown in Figure 8.
P[0]
PIXEL
PERIOD
RG
H1/H3
RGf[12]
P[48] = P[0]
Hf[24]
SHP[28]
CCD SIGNAL
P[24]
P[12]
P[36]
Hr[0]
RGr[0]
SHD[48]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
POSITION
tS1
Figure 6. High-Speed Clock Default and Programmable Locations
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Register Name
Length
Range
Description
POL
1b
High/Low
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
POSLOC
6b
0–47 Edge Location
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
NEGLOC
6b
0–47 Edge Location
Negative Edge Location for H1, H3, and RG
DRV
3b
0–7 Current Steps
Drive Current for H1–H4 and RG Outputs (3.5 mA Per Step)
Table III. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
0 to 11
0 to 11
000000 to 001011
II
12 to 23
16 to 27
010000 to 011011
III
24 to 35
32 to 43
100000 to 101011
IV
36 to 47
48 to 59
110000 to 111011



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