AD9849 datasheet(26/36 Pages) AD

26 / 36 page

REV. 0

AD9848/AD9849

–26–

ANALOG FRONT END DESCRIPTION AND OPERATION

The AD9848/AD9849 signal processing chain is shown in

Figure 15. Each processing step is essential in achieving a high-

quality image from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1

µF series coupling

capacitor. This restores the dc level of the CCD signal to

approximately 1.5 V, to be compatible with the 3 V analog

supply signal of the AD9848/AD9849.

Correlated Double Sampler

The CDS circuit samples each CCD pixel twice to extract the

video information and reject low-frequency noise. The timing

shown in Figure 6 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and data level of the CCD signal respectively. The place-

ment of the SHP and SHD sampling edges is determined by

the setting of the SHPPOSLOC and SHDPOSLOC registers

located at addr. 0xF0 and 0xF1 respectively. Placement of

these two clock signals is critical in achieving the best perfor-

mance from the CCD.

Input Clamp

A line-rate input clamping circuit is used to remove the CCD’s

optical black offset. This offset exists in the CCD’s shielded black

reference pixels. The AD9848/AD9849 removes this offset in

the input stage to minimize the effect of a gain change on the

system black level, usually called the “gain step.” Another

advantage of removing this offset at the input stage is to maxi-

mize system headroom. Some area CCDs have large black

level offset voltages, which, if not corrected at the input stage,

can significantly reduce the available headroom in the inter-

nal circuitry when higher VGA gain settings are used.

Horizontal timing examples are shown on the last page of the

“Applications Information” section. It is recommended that the

CLPDM pulse be used during valid CCD dark pixels. CLPDM

may be used during the optical black pixels, either together with

CLPOB or separately. The CLPDM pulse should be a minimum

of four pixels wide.

PxGA

The PxGA provides separate gain adjustment for the individual

color pixels. A programmable gain amplifier with four separate

values, the PxGA has the capability to “multiplex” its gain value

on a pixel-to-pixel basis (see Figure 17). This allows lower out-

put color pixels to be gained up to match higher output color

pixels. Also, the PxGA may be used to adjust the colors for

white balance, reducing the amount of digital processing that is

needed. The four different gain values are switched according to

the “Color Steering” circuitry. Seven different color steering

modes for different types of CCD color filter arrays are pro-

grammed in the AD9848/AD9849 AFE Register, ctlmode, at

addr. 0x06 (see Figure 16a–16g for timing examples). For

example, Mosaic Separate steering mode accommodates the

popular “Bayer” arrangement of Red, Green, and Blue filters

(see Figure 18).

0.1 F

1.0 F

0.1 F

0dB TO 36dB

CLPDM

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

VGA

8-BIT

DAC

CLAMP LEVEL

VGA GAIN

CDS

INTERNAL

VREF

2V FULL SCALE

–2dB TO +10dB

10/12

PRECISION

TIMING

GENERATION

BYP1

BYP 2

SHP

SHD

PxGA

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

CLPDM CLPOB PBLK

PBLK

1.0V

2.0V

DOUT

BYP 3

INPUT OFFSET

CLAMP

CML

AVDD

INTERNAL

BIASING

AD9848/AD9849

10-/12-BIT

ADC

Figure 15. Analog Front-End Block Diagram

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