PRELIMINARY TECHNICAL DATA

REV. PrC.

ADE7757

–12–

For the purpose of calibration, this integration time could

be 10 to 20 seconds in order to accumulate enough pulses

to ensure correct averaging of the frequency. In normal

operation the integration time could be reduced to one or

two seconds depending, for example, on the required up-

date rate of a display. With shorter integration times on

the MCU the amount of energy in each update may still

have some small amount of ripple, even under steady load

conditions. However, over a minute or more the measured

energy will have no ripple.

Power Measurement Considerations

Calculating and displaying power information will always

have some associated ripple that will depend on the inte-

gration period used in the MCU to determine average

power and also the load. For example, at light loads the

output frequency may be 10 Hz. With an integration pe-

riod of two seconds, only about 20 pulses will be counted.

The possibility of missing one pulse always exists as the

ADE7757 output frequency is running asynchronously to

the MCU timer. This would result in a one-in-twenty or

5% error in the power measurement.

TRANSFER FUNCTION

Frequency Outputs F1 and F2

The ADE7757 calculates the product of two voltage signals (on

Channel V1 and Channel V2) and then low-pass filters this

product to extract real power information. This real power

information is then converted to a frequency. The frequency

information is output on F1 and F2 in the form of active low

pulses. The pulse rate at these outputs is relatively low,

e.g., 0.175 Hz maximum for ac signals with S0 = S1 =

0—see Table II. This means that the frequency at these

outputs is generated from real power information accumu-

lated over a relatively long period of time. The result is an

output frequency that is proportional to the average real

power. The averaging of the real power signal is implicit

to the digital-to-frequency conversion. The output fre-

quency or pulse rate is related to the input voltage signals

by the following equation:

2

4

1

2

1

84

515

ref

rms

rms

V

F

V

V

Freq

−

×

×

×

=

.

where:

rms

V1

= Differential rms voltage signal on Channel V1

(volts)

rms

V 2

= Differential rms voltage signal on Channel V2

(volts)

ref

V

= The reference voltage (2.5 V ± 8%) (volts)

4

1

−

F

= One of four possible frequencies selected by us-

ing the logic inputs S0 and S1—see Table I.

S1

S0

0

0

0.85

0

1

1.7

1

0

3.4

1

1

6.8

NOTE

Example

In this example, with ac voltages of ±30 mV peak applied

to V1 and ±165 mV peak applied to V2, the expected

output frequency is calculated as follows:

4

1

−

F

= 0.85 Hz, S0 = S1 = 0

rms

V1

= 0.03

/

rms

V 2

ref

V

= 2.5 V (nominal reference value).

NOTE: If the on-chip reference is used, actual

output frequencies may vary from device to device

due to reference tolerance of ±8%.

175

0

5

2

2

2

85

0

165

0

03

0

85

515

2

.

.

.

.

.

.

=

×

×

×

×

×

=

Freq

Table II. Maximum Output Frequency on F1 and F2

Max Frequency

S1

S0

for AC Inputs (Hz)

0

0

0.175

0

1

0.35

1

0

0.7

1

1

1.4

Frequency Output CF

The pulse output CF (Calibration Frequency) is intended for

calibration purposes. The output pulse rate on CF can be up to

frequency selected, the higher the CF scaling (except for the

high frequency mode SCF = 0, S1 = S0 = 1). Table III shows

how the two frequencies are related, depending on the states of

the logic inputs S0, S1 and SCF. Due to its relatively high

pulse rate, the frequency at CF logic output is proportional to

the instantaneous real power. As with F1 and F2, CF is derived

from the output of the low-pass filter after multiplication. How-

ever, because the output frequency is high, this real power

information is accumulated over a much shorter time. Hence

less averaging is carried out in the digital-to-frequency con-

version. With much less averaging of the real power signal, the

CF output is much more responsive to power fluctua-

tions—see Signal Processing Block in Figure 11.