MMDF2C02HD

5

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

N–Channel

P–Channel

VGS = 0 V

TJ = 125°C

100

°C

1

100

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

10

0

5

10

15

20

0

4

8

20

1

100

1000

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

VGS = 0 V

TJ = 125°C

10

12

16

25

°C

100

°C

Figure 6. Drain–To–Source Leakage

Current versus Voltage

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (

∆t) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used. In most cases, a satisfactory estimate of average input

current (IG(AV)) can be made from a rudimentary analysis of

the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a resis-

tive load, VGS remains virtually constant at a level known as

the plateau voltage, VSGP. Therefore, rise and fall times may

be approximated by the following:

tr = Q2 x RG/(VGG – VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn–on and turn–off delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG – VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off–state condition when cal-

culating td(on) and is read at a voltage corresponding to the

on–state when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring which is

common to both the drain and gate current paths, produces a

voltage at the source which reduces the gate drive current.

The voltage is determined by Ldi/dt, but since di/dt is a func-

tion of drain current, the mathematical solution is complex.

The MOSFET output capacitance also complicates the

mathematics. And finally, MOSFETs have finite internal gate

resistance which effectively adds to the resistance of the

driving source, but the internal resistance is difficult to mea-

sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is

affected by the parasitic circuit elements. If the parasitics

were not present, the slope of the curves would maintain a

value of unity regardless of the switching speed. The circuit

used to obtain the data is constructed to minimize common

inductance in the drain and gate circuit loops and is believed

readily achievable with board mounted components. Most

power electronic loads are inductive; the data in the figure is

taken with a resistive load, which approximates an optimally

snubbed inductive load. Power MOSFETs may be safely op-

erated into an inductive load; however, snubbing reduces

switching losses.