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STM32F107VC 数据表(PDF) 93 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 93 Page - STMicroelectronics |
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93 / 103 page  STM32F105xx, STM32F107xx Application block diagrams Doc ID 15274 Rev 6 93/104 Figure 50. RMII with a 50 MHz oscillator 1. HCLK must be greater than 25 MHz. Figure 51. RMII with a 25 MHz crystal and PHY with PLL 1. HCLK must be greater than 25 MHz. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 50 MHz RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32F107xx OSC 50 MHz TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins ai15657 /2 or /20 synchronous 2.5 or 25 MHz 50 MHz 50 MHz MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 25 MHz RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32F107xx TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins ai15658 /2 or /20 synchronous 2.5 or 25 MHz 50 MHz XTAL 25 MHz OSC PLL REF_CLK |
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