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STM32F107VC 数据表(PDF) 96 Page - STMicroelectronics |
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STM32F107VC 数据表(HTML) 96 Page - STMicroelectronics |
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96 / 103 page  Application block diagrams STM32F105xx, STM32F107xx 96/104 Doc ID 15274 Rev 6 A.4 USB OTG FS interface + Ethernet/I2S interface solutions With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the Ethernet (MII/RMII) interfaces. Figure 55 illustrate the solution. Figure 55. USB OTG FS + Ethernet solution With the clock tree implemented on the STM32F107xx, only one crystal is required to work with both the USB (host/device/OTG) and the I2S (Audio) interfaces. Figure 56 illustrate the solution. Figure 56. USB OTG FS + I2S (Audio) solution STM32F107 MCU PLL2MUL x8 PLLMUL x9 PLL3MUL x10 Ethernet PHY I2S Sel Sel 25 MHz XTAL Div by 5 MCO SYSCLK Up to 72 MHz PLLVCO (2 xPLLCLK USB PHY OTG 48 MHz Div by 3 Div by 5 Up to 50 MHz 2% accuracy STM32F105 /STM32F107MCU PLL2MUL x8 PLLMUL x6.5 PLL3MUL x20 Ethernet PHY I2S Sel 14.7456 MHz XTAL Div by 4 MCO SYSCLK Up to 71.88 MHz PLLVCO (2 xPLLCLK USB PHY OTG 47.9232 MHz Div by 3 Div by 4 Up to 147.456 MHz Less than 0.5% accuracy 0.16% accuracy MCLK SCLK on MCLK and SCLK PLL3VCO (2 xPLL3CLK |
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