STM32F107VC datasheet(102/103 Pages) STMICROELECTRONICS

102 / 103 page

Revision history

STM32F105xx, STM32F107xx

102/104

Doc ID 15274 Rev 6

11-May-2010

Added BGA package.

Table 5: Pin definitions:

ETH_RMII_RXD0 and ETH_RMII_RXD1 added in remap column for

PD9 and PD10, respectively.

Note added to ETH_MII_RX_DV, ETH_MII_RXD0, ETH_MII_RXD1,

ETH_MII_RXD2 and ETH_MII_RXD3

Updated Table 36: I/O static characteristics on page 55

Added Figure 18: Standard I/O input characteristics - CMOS port

to Figure 21: 5 V tolerant I/O input characteristics - TTL port

Updated Table 43: SPI characteristics on page 65.

Updated Table 44: I2S characteristics on page 68.

Updated Table 48: Ethernet DC electrical characteristics on page 71.

Updated Table 49: Dynamic characteristics: Ethernet MAC signals

for SMI on page 71.

Updated Table 50: Dynamic characteristics: Ethernet MAC signals

for RMII on page 72

Updated Figure 55: USB OTG FS + Ethernet solution on page 96.

Updated Figure 56: USB OTG FS + I2S (Audio) solution on page 96

01-Aug-2011

Changed SRAM size to 64 KB on all parts.

Updated PD0 and PD1 description in Table 5: Pin definitions on

page 26

Updated footnotes below Table 6: Voltage characteristics on page 34

and Table 7: Current characteristics on page 34

Updated tw min in Table 20: High-speed external user clock

characteristics on page 45

Updated startup time in Table 23: LSE oscillator characteristics

(fLSE = 32.768 kHz) on page 48

Added Section 5.3.12: I/O current injection characteristics on

page 55

Updated Table 36: I/O static characteristics on page 55

Add Interna code V to Table 62: Ordering information scheme on

page 89

Table 65.

Document revision history (continued)

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