ADP5052ACPZ-R7 datasheet(17/40 Pages) AD

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Data Sheet

ADP5052

Rev. 0 | Page 17 of 40

THEORY OF OPERATION

The ADP5052 is a micropower management unit that combines

four high performance buck regulators with a 200 mA low dropout

(LDO) regulator in a 48-lead LFCSP package to meet demanding

performance and board space requirements. The device enables

direct connection to high input voltages up to 15 V with no pre-

regulators to make applications simpler and more efficient.

BUCK REGULATOR OPERATIONAL MODES

PWM Mode

In pulse-width modulation (PWM) mode, the buck regulators

in the ADP5052 operate at a fixed frequency; this frequency is

set by an internal oscillator that is programmed by the RT pin.

At the start of each oscillator cycle, the high-side MOSFET turns

on and sends a positive voltage across the inductor. The inductor

current increases until the current-sense signal exceeds the peak

inductor current threshold that turns off the high-side MOSFET;

this threshold is set by the error amplifier output.

During the high-side MOSFET off time, the inductor current

decreases through the low-side MOSFET until the next oscillator

clock pulse starts a new cycle. The buck regulators in the ADP5052

regulate the output voltage by adjusting the peak inductor current

threshold.

PSM Mode

To achieve higher efficiency, the buck regulators in the ADP5052

smoothly transition to variable frequency power save mode (PSM)

operation when the output load falls below the PSM current

threshold. When the output voltage falls below regulation, the

buck regulator enters PWM mode for a few oscillator cycles until

the voltage increases to within regulation. During the idle time

between bursts, the MOSFET turns off, and the output capacitor

supplies all the output current.

The PSM comparator monitors the internal compensation node,

which represents the peak inductor current information. The

average PSM current threshold depends on the input voltage

(VIN), the output voltage (VOUT), the inductor, and the output

capacitor. Because the output voltage occasionally falls below

regulation and then recovers, the output voltage ripple in PSM

operation is larger than the ripple in the forced PWM mode of

operation under light load conditions.

Forced PWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in PWM

mode using the SYNC/MODE pin. In forced PWM (FPWM)

mode, the regulator continues to operate at a fixed frequency

even when the output current is below the PWM/PSM threshold.

In PWM mode, efficiency is lower compared to PSM mode under

light load conditions. The low-side MOSFET remains on when

the inductor current falls to less than 0 A, causing the ADP5052

to enter continuous conduction mode (CCM).

The buck regulators can be configured to operate in automatic

PWM/PSM mode using the SYNC/MODE pin. In automatic

PWM/PSM mode, the buck regulators operate in either PWM

mode or PSM mode, depending on the output current. When the

average output current falls below the PWM/PSM threshold,

the buck regulator enters PSM mode operation; in PSM mode,

the regulator operates with a reduced switching frequency to

maintain high efficiency. The low-side MOSFET turns off when

the output current reaches 0 A, causing the regulator to operate

in discontinuous mode (DCM).

When the SYNC/MODE pin is connected to VREG, the part

operates in forced PWM (FPWM) mode. When the SYNC/

MODE pin is connected to ground, the part operates in auto-

matic PWM/PSM mode.

ADJUSTABLE AND FIXED OUTPUT VOLTAGES

The ADP5052 provides adjustable and fixed output voltage

settings via factory fuse. For the adjustable output settings, use

an external resistor divider to set the desired output voltage via

the feedback reference voltage (0.8 V for Channel 1 to Channel 4,

and 0.5 V for Channel 5).

For the fixed output settings, the feedback resistor divider is

built into the ADP5052, and the feedback pin (FBx) must be tied

directly to the output. Table 7 lists the available fixed output

voltage ranges for each buck regulator channel.

Table 7. Fixed Output Voltage Ranges

Channel

Fixed Output Voltage Range

Channel 1

0.85 V to 1.6 V in 25 mV steps

Channel 2

3.3 V to 5.0 V in 300 mV or 200 mV steps

Channel 3

1.2 V to 1.8 V in 100 mV steps

Channel 4

2.5 V to 5.5 V in 100 mV steps

The output range can also be programmed by factory fuse. If

a different output voltage range is required, contact your local

Analog Devices, Inc., sales or distribution representative.

INTERNAL REGULATORS (VREG AND VDD)

The internal VREG regulator in the ADP5052 provides a stable

5.1 V power supply for the bias voltage of the MOSFET drivers.

The internal VDD regulator in the ADP5052 provides a stable

3.3 V power supply for internal control circuits. Connect a 1.0 µF

ceramic capacitor between VREG and ground; connect another

1.0 µF ceramic capacitor between VDD and ground. The internal

VREG and VDD regulators are active as long as PVIN1 is available.

The internal VREG regulator can provide a total load of 95 mA

including the MOSFET driving current, and it can be used as

an always alive 5.1 V power supply for a small system current

demand. The current-limit circuit is included in the VREG

regulator to protect the circuit when the part is heavily loaded.

The VDD regulator is for internal circuit use and is not recom-

mended for other purposes.

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