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ADP5052

Data Sheet

Rev. 0 | Page 18 of 40

SEPARATE SUPPLY APPLICATIONS

The ADP5052 supports separate input voltages for the four

buck regulators. This means that the input voltages for the four

buck regulators can be connected to different supply voltages.

The PVIN1 voltage provides the power supply for the internal

regulators and the control circuitry. Therefore, if the user plans

to use separate supply voltages for the buck regulators, the PVIN1

voltage must be above the UVLO threshold before the other

channels begin to operate.

Precision enabling can be used to monitor the PVIN1 voltage

and to delay the startup of the outputs to ensure that PVIN1

is high enough to support the outputs in regulation. For more

information, see the Precision Enabling section.

The ADP5052 supports cascading supply operation for the four

buck regulators. As shown in Figure 37, PVIN2, PVIN3, and

PVIN4 are powered from the Channel 1 output. In this config-

uration, the Channel 1 output voltage must be higher than the

UVLO threshold for PVIN2, PVIN3, and PVIN4.

PVIN1

BUCK 1

BUCK 2

VOUT1

PVIN2

PVIN4

VOUT2 TO VOUT4

VIN

Figure 37. Cascading Supply Application

LOW-SIDE DEVICE SELECTION

The buck regulators in Channel 1 and Channel 2 integrate 4 A

high-side power MOSFETs and low-side MOSFET drivers. The

N-channel MOSFETs selected for use with the ADP5052 must be

able to work with the synchronized buck regulators. In general,

a low RDSON N-channel MOSFET can be used to achieve higher

efficiency; dual MOSFETs in one package (for both Channel 1 and

Channel 2) are recommended to save space on the PCB. For more

information, see the Low-Side Power Device Selection section.

BOOTSTRAP CIRCUITRY

Each buck regulator in the ADP5052 has an integrated bootstrap

regulator. The bootstrap regulator requires a 0.1 µF ceramic capac-

itor (X5R or X7R) between the BSTx and SWx pins to provide

the gate drive voltage for the high-side MOSFET.

ACTIVE OUTPUT DISCHARGE SWITCH

Each buck regulator in the ADP5052 integrates a discharge switch

from the switching node to ground. This switch is turned on when

its associated regulator is disabled, which helps to discharge the

output capacitor quickly. The typical value of the discharge switch

is 250 Ω for Channel 1 to Channel 4. The discharge switch func-

tion can be enabled or disabled for all four buck regulators by

factory fuse.

PRECISION ENABLING

The ADP5052 has an enable control pin for each regulator,

including the LDO regulator. The enable control pin (ENx) features

a precision enable circuit with a 0.8 V reference voltage. When

the voltage at the ENx pin is greater than 0.8 V, the regulator is

enabled. When the voltage at the ENx pin falls below 0.725 V,

the regulator is disabled. An internal 1 MΩ pull-down resistor

prevents errors if the ENx pin is left floating.

The precision enable threshold voltage allows easy sequencing

of channels within the part, as well as sequencing between the

ADP5052 and other input/output supplies. The ENx pin can also

be used as a programmable UVLO input using a resistor divider

(see Figure 38). For more information, see the Programming

the UVLO Input section.

0.8V

DEGLITCH

TIMER

INTERNAL

ENABLE

ENx

1MΩ

INPUT/OUTPUT

VOLTAGE

ADP5052

Figure 38. Precision Enable Diagram for One Channel

OSCILLATOR

The switching frequency (fSW) of the ADP5052 can be set to

a value from 250 kHz to 1.4 MHz by connecting a resistor

from the RT pin to ground. The value of the RT resistor can

be calculated as follows:

RRT (kΩ) = [14,822/fSW (kHz)]1.081

Figure 39 shows the typical relationship between the switching

frequency (fSW) and the RT resistor. The adjustable frequency

allows users to make decisions based on the trade-off between

efficiency and solution size.

1.6M

1.4M

1.2M

1.0M

800k

600k

400k

200k

RT RESIST

OR (kΩ)

Figure 39. Switching Frequency vs. RT Resistor

For Channel 1 and Channel 3, the frequency can be set to half the

master switching frequency set by the RT pin. This setting can be

selected by factory fuse. If the master switching frequency is less

than 250 kHz, this halving of the frequency for Channel 1 or

Channel 3 is not recommended.

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