ADP5052ACPZ-R7 datasheet(22/40 Pages) AD

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ADP5052

Data Sheet

Rev. 0 | Page 22 of 40

UNDERVOLTAGE LOCKOUT (UVLO)

Undervoltage lockout circuitry monitors the input voltage level of

each buck regulator in the ADP5052. If any input voltage (PVINx

pin) falls below 3.78 V (typical), the corresponding channel is

turned off. After the input voltage rises above 4.2 V (typical), the

soft start period is initiated, and the corresponding channel is

enabled when the ENx pin is high.

Note that a UVLO condition on Channel 1 (PVIN1 pin) has

a higher priority than a UVLO condition on other channels,

which means that the PVIN1 supply must be available before

other channels can be operated.

POWER-GOOD FUNCTION

The ADP5052 includes an open-drain power-good output

(PWRGD pin) that becomes active high when the selected buck

regulators are operating normally. By default, the PWRGD pin

monitors the output voltage on Channel 1. Other channels can

be configured to control the PWRGD pin when the ADP5052

is ordered (see Table 19).

A logic high on the PWRGD pin indicates that the regulated

output voltage of the buck regulator is above 90.5% (typical) of

its nominal output. When the regulated output voltage of the

buck regulator falls below 87.2% (typical) of its nominal output

for a delay time greater than approximately 50 µs, the PWRGD

pin goes low.

The output of the PWRGD pin is the logical AND of the internal

PWRGx signals. An internal PWRGx signal must be high for a

validation time of 1 ms before the PWRGD pin goes high; if one

PWRGx signal fails, the PWRGD pin goes low with no delay. The

channels that control the PWRGD pin (Channel 1 to Channel 4)

can be specified by factory fuse. The default PWRGD setting is

to monitor the output of Channel 1.

THERMAL SHUTDOWN

If the ADP5052 junction temperature exceeds 150°C, the thermal

shutdown circuit turns off the IC except for the internal linear

regulators. Extreme junction temperatures can be the result of

high current operation, poor circuit board design, or high ambient

temperature. A 15°C hysteresis is included so that the ADP5052

does not return to operation after thermal shutdown until the

on-chip temperature falls below 135°C. When the part exits ther-

mal shutdown, a soft start is initiated for each enabled channel.

LDO REGULATOR

The ADP5052 integrates a general-purpose LDO regulator with

low quiescent current and low dropout voltage. The LDO regu-

lator provides up to 200 mA of output current.

The LDO regulator operates with an input voltage of 1.7 V to

5.5 V. The wide supply range makes the regulator suitable for

cascading configurations where the LDO supply voltage is

provided from one of the buck regulators. The LDO output

voltage is set using an external resistor divider (see Figure 48).

LDO

FB5

VOUT5

EN5

PVIN5

1µF

1.7V TO 5.5V

Figure 48. 200 mA LDO Regulator

The LDO regulator provides a high power supply rejection ratio

(PSRR), low output noise, and excellent line and load transient

response using small 1 µF ceramic input and output capacitors.

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