LSM330DLCTR datasheet(55/66 Pages) STMICROELECTRONICS

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LSM330DLC

Doc ID 022162 Rev 2

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8.29

CTRL_REG3_G (22h)

8.30

CTRL_REG4_G (23h)

1000

0.018

0.045

0.09

0.18

1001

0.009

0.018

0.045

0.09

Table 75.

High-pass filter cut-off frequency configuration [Hz] (continued)

Table 76.

CTRL_REG3_G register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 77.

CTRL_REG3_G description

I1_Int1

Interrupt enable on INT1_G pin. Default value 0. (0: Disable; 1: Enable)

I1_Boot

Boot status available on INT1_G. Default value 0. (0: Disable; 1: Enable)

H_Lactive

Interrupt active configuration on INT1_G. Default value 0. (0: High; 1:Low)

PP_OD

Push-pull / Open drain. Default value: 0. (0: Push-pull; 1: Open drain)

I2_DRDY

Date ready on DRDY_G/INT2_G. Default value 0. (0: Disable; 1: Enable)

I2_WTM

FIFO watermark interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Ena-

ble)

I2_ORun

FIFO overrun interrupt on DRDY_G/INT2_G Default value: 0. (0: Disable; 1: Enable)

I2_Empty

FIFO empty interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable)

Table 78.

CTRL_REG4_G register

BDU

BLE

FS1

FS0

SIM

Table 79.

CTRL_REG4_G description

BDU

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSb and LSb

reading)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSb @ lower address; 1: Data MSb @ lower address)

FS1-FS0

Full scale selection. Default value: 00

(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

SIM

3-wire SPI Serial interface read mode enable. Default value: 0

(0: 3-wire Read mode disabled; 1: 3-wire read enabled).

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